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參數(shù)資料
| 型號(hào)： | TPS51317RGBT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING REGULATOR, 1500 kHz SWITCHING FREQ-MAX, PQCC20 |
| 封裝： | 4 X 3.50 MM, GREEN, PLASTIC, QFN-20 |
| 文件頁(yè)數(shù)： | 12/28頁(yè) |
| 文件大小： | 1000K |
| 代理商： | TPS51317RGBT |
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SLUSAH9
– MARCH 2011
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Table 1. ORDERING INFORMATION(1)
MINIMUM
TA
PACKAGE(2)
ORDERING NUMBER
PINS
OUTPUT SUPPLY
ECO PLAN
QUANTITY
TPS51317RGBR
20
Tape and reel
3000
Green (RoHS and
Plastic QFN
-40
°C to 85°C
no Pb/Br)
(RGB)
TPS51317RGBT
20
Mini reel
250
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the TI
website at www.ti.com.
(2)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
THERMAL INFORMATION
TPS51317
THERMAL METRIC(1)
RGB
UNITS
20 PINS
θJA
Junction-to-ambient thermal resistance(2)
35.5
θJCtop
Junction-to-case (top) thermal resistance(3)
39.6
θJB
Junction-to-board thermal resistance(4)
12.4
°C/W
ψJT
Junction-to-top characterization parameter(5)
0.5
ψJB
Junction-to-board characterization parameter(6)
12.5
θJCbot
Junction-to-case (bottom) thermal resistance(7)
3.7
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3)
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5)
The junction-to-top characterization parameter,
ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6)
The junction-to-board characterization parameter,
ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7)
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
2
Copyright
2011, Texas Instruments Incorporated
Product Folder Link(s): TPS51317
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