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參數(shù)資料
| 型號： | TPS53114PWR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, 700 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | TSSOP-16 |
| 文件頁數(shù)： | 25/27頁 |
| 文件大小： | 912K |
| 代理商： | TPS53114PWR |
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SW
DRVL
DRVH
VBST
EN
VO
VFB
GND
FSEL
VREG5
TRIP
PGND
VO
7
15
5
12
13
14
6
10
9
11
1
2
4
16
VIN
V5FILT
8
CER
VIN
5VREG
EN
Logic
LL
PGND
SSLogic
UV
OV
Protection
Logic
Ref
SS
UV
OV
UVLO
TEST
TESTBLOCK
REF
TSD
Ref
3
SS
PowerGood
FSELECT
-30%
15%
PGND
OCP
GND
10 A
m
XCON
ControlLogic
VREG5
0.1 F
m
10x2 F
m
4.7 F
m
1 F
m
PWM
www.ti.com
SLVS887B – APRIL 2009 – REVISED OCTOBER 2010
FUNCTIONAL BLOCK DIAGRAM
DETAILED DESCRIPTION
PWM OPERATION
The main control loop of the TPS53114 is an adaptive on-time pulse width modulation (PWM) controller using a
proprietary D-CAP2 mode control. D-CAP2 mode control combines constant on-time control with an internal
compensation circuit for pseudo-fixed frequency and low external component count configuration with both low
ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. After an internal one-shot timer expires, this
MOSFET is turned off. The one-shot timer is reset and the high-side MOSFET is turned back on when the
feedback voltage falls below the reference voltage. The one shot is set by the converter input voltage VIN, and
the output voltage VO, to maintain a pseudo-fixed frequency over the input voltage range, hence it is called
adaptive on-time control. An internal ramp is added to the reference voltage to simulate output ripple, eliminating
the need for ESR induced output ripple from D-CAP mode control.
DRIVERS
The TPS53114 contains two high-current resistive MOSFET gate drivers. The low-side driver is a ground
referenced, VREG5 powered driver designed to drive the gate of a high-current, low RDS(on) N-channel MOSFET
whose source is connected to PGND. The high-side driver is a floating SW referenced VBST powered driver
designed to drive the gate of a high-current, low RDS(on) N-channel MOSFET. To maintain the VBST voltage
during the high-side driver ON time, a capacitor is placed from SW to VBST. Each driver draws average current
equal to gate charge (Qg at Vgs = 5 V) times switching frequency (fSW).
To prevent cross-conduction, there is a narrow dead-time when both high-side and low-side drivers are OFF
between each driver transition. During this time the inductor current is carried by one of the MOSFET's body
diodes.
Copyright 2009–2010, Texas Instruments Incorporated
7
Product Folder Link(s) :TPS53114
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