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參數資料
| 型號： | TPS54073PWP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩壓器 |
| 英文描述： | 25 A SWITCHING REGULATOR, 762 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | GREEN, PLASTIC, HTSSOP-28 |
| 文件頁數： | 22/26頁 |
| 文件大?。?/td> | 850K |
| 代理商： | TPS54073PWP |
DEVICE INFORMATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AGND
VSENSE
COMP
PWRGD
BOOT
PH
RT
SYNC
SS/ENA
VBIAS
VIN
PVIN
PGND
THERMAL
PAD
www.ti.com ............................................................................................................................................................................................ SLVS547 – FEBRUARY 2005
PWP PACKAGE
(TOP VIEW)
TERMINAL FUNCTIONS
PIN NAME
PIN NUMBER
DESCRIPTION
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, and
AGND
1
RT resistor. If using the PowerPAD, connect it to AGND. See the Application Information section for
details.
Bootstrap output. 0.022-
F to 0.1-F low-ESR capacitor connected from BOOT to PH generates floating
BOOT
5
drive for the high-side FET driver.
COMP
3
Error amplifier output. Connect frequency compensation network from COMP to VSENSE
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large
15, 16, 17, 18,
PGND
copper areas to the input and output supply returns, and negative terminals of the input and output
19
capacitors. A single point connection to AGND is recommended.
PH
6-14
Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
Input supply for the power MOSFET switches and internal bias regulator. Bypass the PVIN pins to the
PVIN
20, 21, 22, 23
PGND pins close to device package with a high-quality, low-ESR 10-
F ceramic capacitor.
Power-good open-drain output. High when VSENSE > 90% Vref, otherwise PWRGD is low. Note that
PWRGD
4
output is low when SS/ENA is low or the internal shutdown signal is active.
RT
28
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs.
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device
SS/ENA
26
operation and capacitor input to externally set the start-up time.
Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator
SYNC
27
or pin select between two internally set switching frequencies. When used to synchronize to an external
signal, a resistor must be connected to the RT pin.
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND
VBIAS
25
pin with a high-quality, low-ESR 0.1-
F to 1.0-F ceramic capacitor.
Input supply for the internal control circuits. Bypass the VIN pin to the PGND pins close to device package
VIN
24
with a high-quality, low-ESR 1-
F ceramic capacitor.
VSENSE
2
Error amplifier inverting input. Connect to output voltage compensation network/output divider.
Copyright 2005, Texas Instruments Incorporated
5
Product Folder Link(s): TPS54073
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