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參數(shù)資料
| 型號(hào)： | TPS54073PWP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 25 A SWITCHING REGULATOR, 762 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | GREEN, PLASTIC, HTSSOP-28 |
| 文件頁數(shù)： | 26/26頁 |
| 文件大?。?/td> | 850K |
| 代理商： | TPS54073PWP |
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Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance
Minimum Recommended Top
Side Analog Ground Area
0.3478
0.0150
0.06
0.0256
0.1700
0.1340
0.0630
0.0400
0.0180
4 PL
0.2090
0.0130
8 PL
Minimum Recommended Exposed
Copper Area for PowerPAD. 5mm
Stencils May Require 10 Percent
Larger Area
0.0650
0.0500
0.0650
0.0339
0.0500
Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside
PowerPAD Area 4 x 0.018 Diameter Under Device as Shown.
Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground
Area Is Extended.
0.3820
www.ti.com ............................................................................................................................................................................................ SLVS547 – FEBRUARY 2005
Connect the output filter capacitor(s) between the
For operation at full rated load current, the analog
VOUT trace and PGND. It is important to keep the
ground
plane
must
provide
an
adequate
loop formed by the PH pins, Lout, Cout, and PGND
heat-dissipating area. A 3-inch by 3-inch plane of
as small as is practical. Place the compensation
1-ounce
copper
is
recommended,
though
not
components from the VOUT trace to the VSENSE
mandatory, depending on ambient temperature and
and COMP pins. Do not place these components too
airflow. Most applications have larger areas of
close to the PH trace. Due to the size of the IC
internal ground plane available, and the PowerPAD
package and the device pinout, they must be routed
must be connected to the largest area available.
close, but maintain as much separation as possible
Additional areas on the top or bottom layers also help
while keeping the layout compact. Connect the bias
dissipate heat, and any area available must be used
capacitor from the VBIAS pin to analog ground using
when 6-A or greater operation is desired. Connection
the isolated analog ground trace. If a slow-start
from the exposed area of the PowerPAD to the
capacitor or RT resistor is used, or if the SYNC pin is
analog ground plane layer must be made using
used to select 350-kHz operating frequency, connect
0.013-inch diameter vias to avoid solder wicking
them to this trace.
through the vias.
Optional
prebias
diodes
should
be
connected
Eight vias must be in the PowerPAD area with four
between the output voltage trace and the prebias
additional vias located under the device package. The
source. The source is VIN, PVIN, or some other
size of the vias under the package, but not in the
voltage
rail.
This
is
dependent
on
the
user's
exposed thermal pad area, can be increased to
application circuit. In some cases, the diodes are not
0.018.
Additional
vias
beyond
the
twelve
required if the prebias voltage is caused by an
recommended that enhance thermal performance
external load circuit leakage path.
must be included in areas not under the device
package.
Figure 11. Recommended Land Pattern for 28-Pin PWP PowerPAD
Copyright 2005, Texas Instruments Incorporated
9
Product Folder Link(s): TPS54073
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