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參數(shù)資料
| 型號： | TPS54110PWPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 3.5 A SWITCHING REGULATOR, 762 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封裝： | GREEN, PLASTIC, HTSSOP-20 |
| 文件頁數(shù)： | 13/30頁 |
| 文件大小： | 870K |
| 代理商： | TPS54110PWPG4 |
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W
100 k
SWITCHING FREQUENCY=
500 kHz
R
SLVS500C
– DECEMBER 2003 – REVISED FEBRUARY 2011
(27)
External synchronization of the PWM ramp is possible over the frequency range of 330 kHz to 700 kHz by driving
a synchronization signal into SYNC and connecting a resistor from RT to AGND. Choose an RT resistor that sets
the free-running frequency to 80% of the synchronization signal. Table 3 summarizes the frequency selection
configurations.
Table 3. Summary of the Frequency Selection Configurations
SWITCHING FREQUENCY
SYNC PIN
RT PIN
350 kHz, internally set
Float or AGND
Float
550 kHz, internally set
≥ 2.5 V
Float
Externally set 280 kHz to 700 kHz Float
R = 68 k to 180 k
Externally synchronized
R = RT value for 80% of external
Synchronization signal
frequency
synchronization frequency
Error Amplifier
The high-performance, wide-bandwidth, voltage error amplifier sets the TPS54110 apart from most dc/dc
converters. The user is given the flexibility to use a wide range of output L- and C-filter components to suit the
particular application needs. Type-2 or type-3 compensation can be employed using external compensation
components.
PWM Control
Signals from the error-amplifier output, oscillator, and current-limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the control logic includes the PWM comparator, OR gate, PWM
latch, and portions of the adaptive dead-time and control-logic block. During steady-state operation below the
current-limit threshold, the PWM-comparator output and oscillator pulse train alternately reset and set the PWM
latch. Once the PWM latch is set, the low-side FET remains on for a minimum duration set by the oscillator pulse
duration. During this period, the PWM ramp discharges rapidly to its valley voltage. When the ramp begins to
charge back up, the low-side FET turns off and high-side FET turns on. As the PWM ramp voltage exceeds the
error-amplifier output voltage, the PWM comparator resets the latch, thus turning off the high-side FET and
turning on the low-side FET. The low-side FET remains on until the next oscillator pulse discharges the PWM
ramp.
During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error-amplifier output is high, the PWM latch is never reset and the high-side FET
remains on until the oscillator pulse signals the control logic to turn the high-side FET off and the low-side FET
on. The device operates at its maximum duty cycle until the output voltage rises to the regulation set-point,
setting VSENSE to approximately the same voltage as Vref. If the error-amplifier output is low, the PWM latch is
continually reset and the high-side FET does not turn on. The low-side FET remains on until the VSENSE
voltage decreases to a range that allows the PWM comparator to change states. The TPS54110 is capable of
sinking current continuously until the output reaches the regulation set-point.
If the current-limit comparator remains tripped longer than 100 ns, the PWM latch resets before the PWM ramp
exceeds the error-amplifier output. The high-side FET turns off and low-side FET turns on to decrease the
energy in the output inductor, and consequently the output current. This process is repeated each cycle that the
current-limit comparator is tripped.
Dead-Time Control and MOSFET Drivers
Adaptive dead-time control prevents shoot-through current from flowing in both N-channel power MOSFETs
during the switching transitions by actively controlling the turn-on times of the MOSFET drivers. The high-side
driver does not turn on until the gate-drive voltage to the low-side FET is below 2 V. The low-side driver does not
turn on until the voltage at the gate of the high-side MOSFETs is below 2 V. The high-side and low-side drivers
are designed with 300-mA source and sink capability to quickly drive the power MOSFETs gates. The low-side
driver is supplied from VIN, while the high-side driver is supplied from the BOOT pin. A bootstrap circuit uses an
external BOOT capacitor and an internal 2.5-
Ω bootstrap switch connected between the VIN and BOOT pins.
The integrated bootstrap switch improves drive efficiency and reduces external-component count.
20
2003–2011, Texas Instruments Incorporated
Product Folder Link(s): TPS54110
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TPS54110PWPR | 功能描述:直流/直流開關(guān)調(diào)節(jié)器 1.5A Step Down Converter RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關(guān)頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
| TPS54110PWPRG4 | 功能描述:直流/直流開關(guān)調(diào)節(jié)器 1.5A Step Down Converter RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關(guān)頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
| TPS54110-Q1 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3-V TO 6-V INPUT, 1.5-A OUTPUT SYNCHRONOUS-BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFT?￡a) |
| TPS54110QPWPRQ1 | 功能描述:直流/直流開關(guān)調(diào)節(jié)器 3-6V Input 1.5A Out Synch Buck PWM Swer RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關(guān)頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
| TPS54112PWP | 制造商:Texas Instruments 功能描述: |
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