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參數資料
| 型號： | TPS5420MDREPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩壓器 |
| 英文描述： | 5.2 A SWITCHING REGULATOR, 600 kHz SWITCHING FREQ-MAX, PDSO8 |
| 封裝： | GREEN, PLASTIC, MS-012AA, SOIC-8 |
| 文件頁數： | 22/23頁 |
| 文件大小： | 658K |
| 代理商： | TPS5420MDREPG4 |
www.ti.com
Thermal Shutdown
PCB Layout
SLVS717 – DECEMBER 2006
APPLICATION INFORMATION (continued)
If the sensed current continues increasing, even with the cycle-by-cycle current limiting that may happen during
short circuit or under other circumstances, the hiccup-mode overcurrent protection is triggered instead of the
cycle-by-cycle current limiting. During the hiccup-mode overcurrent protection, the voltage reference is grounded
and the high-side MOSFET is turned off for the hiccup time. Once the hiccup time is complete, the regulator
restarts.
The TPS5420 protects itself from overheating with an internal thermal shutdown circuit. If the junction
temperature exceeds the thermal shutdown trip point, the voltage reference is grounded and the high-side
MOSFET is turned off. The part is restarted under control of the slow start circuit automatically when the junction
temperature drops 14
°C below the thermal shutdown trip point.
Connect a low ESR ceramic bypass capacitor to the VIN pin. Care should be taken to minimize the loop area
formed by the bypass capacitor connections, the VIN pin, and the TPS5420 ground pin. The best way to do this
is to extend the top-side ground area from under the device adjacent to the VIN trace, and place the bypass
capacitor as close as possible to the VIN pin. The minimum recommended bypass capacitance is 10-
F ceramic
with a X5R or X7R dielectric.
There should be a ground area on the top layer directly underneath the IC to connect the GND pin of the device
and the anode of the catch diode. The GND pin should be tied to the PCB ground by connecting it to the ground
area under the device as shown in Figure 9.
The PH pin should be routed to the output inductor, catch diode, and boot capacitor. Since the PH connection is
the switching node, the inductor should be located close to the PH pin, and the area of the PCB conductor
minimized to prevent excessive capacitive coupling. The catch diode should also be placed close to the device
to minimize the output current loop area. Connect the boot capacitor between the phase node and the BOOT pin
as shown. Keep the boot capacitor close to the IC and minimize the conductor trace lengths. The component
placements and connections shown work well, but other connection routings may also be effective.
Connect the output filter capacitor(s) as shown between the VOUT trace and GND. It is important to keep the
loop formed by the PH pin, Lout, Cout, and GND as small as is practical.
Connect the VOUT trace to the VSENSE pin using the resistor divider network to set the output voltage. Do not
route this trace too close to the PH trace. Due to the size of the IC package and the device pinout, the trace may
need to be routed under the output capacitor. The routing may be done on an alternate layer if a trace under the
output capacitor is not desired.
The grounding scheme shown is used via a connection to a different layer to route to the ENA pin.
8
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