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參數資料
| 型號： | TPS54310MPWPREP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩壓器 |
| 英文描述： | 6 A SWITCHING REGULATOR, 775 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封裝： | PLASTIC, HTSSOP-20 |
| 文件頁數： | 5/19頁 |
| 文件大?。?/td> | 487K |
| 代理商： | TPS54310MPWPREP |
VBIAS Regulator (VBIAS)
DETAILED DESCRIPTION
Under Voltage Lock Out (UVLO)
Slow-Start/Enable (SS/ENA)
Voltage Reference
Oscillator and PWM Ramp
SWITCHING FREQUENCY +
100 kW
R
500 kHz
(5)
t
d +
C
(SS)
1.2 V
5 mA
(3)
t
(SS) +
C
(SS)
0.7 V
5 mA
(4)
www.ti.com ..................................................................................................................................................................................................... SLVS818 – APRIL 2008
The VBIAS regulator provides internal analog and
digital blocks with a stable supply voltage over
variations in junction temperature and input voltage. A
The TPS54310 incorporates an under voltage lockout
high quality, low-ESR, ceramic bypass capacitor is
circuit to keep the device disabled when the input
required on the VBIAS pin. X7R or X5R grade
voltage (VIN) is insufficient. During power up, internal
dielectrics are recommended because their values
circuits are held inactive until VIN exceeds the
are more stable over temperature. The bypass
nominal UVLO threshold voltage of 2.95 V. Once the
capacitor should be placed close to the BVIAS pin
UVLO start threshold is reached, device start-up
and returned to AGND. External loading on VBIAS is
begins. The device operates until VIN falls below the
allowed, with the caution that internal circuits require
nominal UVLO stop threshold of 2.8 V. Hysteresis in
a minimum BVIAS of 2.7 V, and external loads on
the UVLO comparator, and a 2.5-s rising and falling
VBIAS with ac or digital switching noise may degrade
edge deglitch circuit reduce the likelihood of shutting
performance. The VBIAS pin may be useful as a
the device down due to noise on VIN.
reference voltage for external circuits.
The slow-start/enable pin provides two functions; first,
The voltage reference system produces a precise Vref
the pin acts as an enable (shutdown) control by
signal by scaling the output of a temperature stable
keeping the device turned off until the voltage
bandgap circuit. During manufacture, the bandgap
exceeds the start threshold voltage of approximately
and scaling circuits are trimmed to produce 0.891 V
1.2 V. When SS/ENA exceeds the enable threshold,
at the output of the error amplifier, with the amplifier
device start up begins. The reference voltage fed to
connected as a voltage follower. The trim procedure
the error amplifier is linearly ramped up from 0 V to
adds
to
the
high
precision
regulation
of
the
0.891 V in 3.35 ms. Similarly, the converter output
TPS54310, since it cancels offset errors in the scale
voltage reaches regulation in approximately 3.35 ms.
and error amplifier circuits
Voltage hysteresis and a 2.5-s falling edge deglitch
circuit reduce the likelihood of triggering the enable
due to noise.
The oscillator frequency can be set to internally fixed
The second function of the SS/ENA pin provides an
values of 350 kHz or 550 kHz using the SYNC pin as
external means of extending the slow-start time with
a static digital input. If a different frequency of
a low-value capacitor connected between SS/ENA
operation is required for the application, the oscillator
and AGND. Adding a capacitor to the SS/ENA pin
frequency can be externally adjusted from 280 kHz to
has two effects on start-up. First, a delay occurs
700 kHz by connecting a resistor to the RT pin to
between release of the SS/ENA pin and start up of
ground and floating the SYNC pin. The switching
the output. The delay is proportional to the slow-start
frequency is approximated by the following equation,
capacitor value and lasts until the SS/ENA pin
where R is the resistance from RT to AGND:
reaches the enable threshold. The start-up delay is
approximately:
External
synchronization
of
the
PWM
ramp
is
possible over the frequency range of 330 kHz to
Second, as the output becomes active, a brief
700 kHz by driving a synchronization signal into
ramp-up at the internal slow-start rate may be
SYNC and connecting a resistor from RT to AGND.
observed before the externally set slow-start rate
Choose an RT resistor that sets the free-running
takes
control
and
the
output
rises
at
a
rate
frequency to 80% of the synchronization signal.
proportional to the slow-start capacitor. The slow-start
summarizes
the
frequency
selection
time set by the capacitor is approximately:
configurations.
The actual slow-start is likely to be less than the
above approximation due to the brief ramp-up at the
internal rate.
Copyright 2008, Texas Instruments Incorporated
13
Product Folder Link(s): TPS54310-EP
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| TPS54310PWP | 功能描述:直流/直流開關調節器 3A Sync Buck Converter RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數量: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
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| TPS54310PWPG4 | 功能描述:直流/直流開關調節器 3A Sync Buck Converter RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數量: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
| TPS54310PWP-P | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
| TPS54310PWPR | 功能描述:直流/直流開關調節器 3A Sync Buck Converter RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數量: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
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