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參數(shù)資料
| 型號： | TPS54310MPWPREP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 6 A SWITCHING REGULATOR, 775 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封裝： | PLASTIC, HTSSOP-20 |
| 文件頁數(shù)： | 6/19頁 |
| 文件大小： | 487K |
| 代理商： | TPS54310MPWPREP |
Error Amplifier
PWM Control
Dead-Time Control and MOSFET Drivers
Overcurrent Protection
SLVS818 – APRIL 2008 ..................................................................................................................................................................................................... www.ti.com
Table 1. Summary of the Frequency Selection Configurations
SWITCHING FREQUENCY
SYNC PIN
RT PIN
350 kHz, internally set
Float or AGND
Float
550 kHz, internally set
≥ 2.5 V
Float
Externally set 280 kHz to 700 kHz
Float
R = 68 k to 180 k
Externally synchronized frequency
Synchronization signal
R = RT value for 80% of external synchronization frequency
The high performance, wide bandwidth, voltage error
low-side FET remains on until the VSENSE voltage
amplifier sets the TPS54310 apart from most dc/dc
decreases
to
a
range
that
allows
the
PWM
converters. The user is given the flexibility to use a
comparator to change states. The TPS54310 is
wide range of output L and C filter components to suit
capable of sinking current continuously until the
the particular needs of the application. Type 2 or type
output reaches the regulation set-point.
3 compensation can be employed using external
If the current limit comparator trips for longer than
compensation components.
100 ns, the PWM latch resets before the PWM ramp
exceeds the error amplifier output. The high-side FET
turns off and low-side FET turns on to decrease the
Signals from the error amplifier output, oscillator, and
energy in the output inductor and consequently the
current limit circuit are processed by the PWM control
output current. This process is repeated each cycle in
logic. Referring to the internal block diagram, the
which the current limit comparator is tripped.
control logic includes the PWM comparator, OR gate,
PWM latch, and portions of the adaptive dead-time
and control logic block. During steady-state operation
Adaptive dead-time control prevents shoot-through
below
the
current
limit
threshold,
the
PWM
current
from
flowing
in
both
N-channel
power
comparator
output
and
oscillator
pulse
train
MOSFETs during the switching transitions by actively
alternately reset and set the PWM latch. Once the
controlling the turn-on times of the MOSFET drivers.
PWM latch is set, the low-side FET remains on for a
The high-side driver does not turn on until the gate
minimum duration set by the oscillator pulse duration.
drive voltage to the low-side FET is below 2 V. The
During this period, the PWM ramp discharges rapidly
low-side driver does not turn on until the voltage at
to its valley voltage. When the ramp begins to charge
the gate of the high-side MOSFETs is below 2 V. The
back up, the low-side FET turns off and high-side
high-side and low-side drivers are designed with
FET turns on. As the PWM ramp voltage exceeds the
300-mA source and sink capability to quickly drive the
error amplifier output voltage, the PWM comparator
power MOSFETs gates. The low-side driver is
resets the latch, thus turning off the high-side FET
supplied from VIN, while the high-side drive is
and turning on the low-side FET. The low-side FET
supplied from the BOOT pin. A bootstrap circuit uses
remains on until the next oscillator pulse discharges
an external BOOT capacitor and an internal 2.5-
the PWM ramp.
bootstrap switch connected between the VIN and
During transient conditions, the error amplifier output
BOOT pins. The integrated bootstrap switch improves
could be below the PWM ramp valley voltage or
drive efficiency and reduces external component
above the PWM peak voltage. If the error amplifier is
count.
high, the PWM latch is never reset and the high-side
FET remains on until the oscillator pulse signals the
control logic to turn the high-side FET off and the
The cycle by cycle current limiting is achieved by
low-side
FET
on.
The
device
operates
at
its
sensing the current flowing through the high-side
maximum duty cycle until the output voltage rises to
MOSFET and differential amplifier and comparing it to
the
regulation
set-point,
setting
VSENSE
to
the preset overcurrent threshold. The high-side
approximately the same voltage as Vref. If the error
MOSFET is turned off within 200 ns of reaching the
amplifier output is low, the PWM latch is continually
current limit threshold. A 100-ns
leading
edge
reset and the high-side FET does not turn on. The
blanking circuit prevents false tripping of the current
limit. Current limit detection occurs only when current
flows from VIN to PH when sourcing current to the
output filter. Load protection during current sink
operation is provided by thermal shutdown.
14
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS54310-EP
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| TPS54310PWP | 功能描述:直流/直流開關(guān)調(diào)節(jié)器 3A Sync Buck Converter RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關(guān)頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
| TPS54310PWP | 制造商:Texas Instruments 功能描述:BUCK PWM REG FET 3A SMD 54310 |
| TPS54310PWPG4 | 功能描述:直流/直流開關(guān)調(diào)節(jié)器 3A Sync Buck Converter RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關(guān)頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
| TPS54310PWP-P | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
| TPS54310PWPR | 功能描述:直流/直流開關(guān)調(diào)節(jié)器 3A Sync Buck Converter RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關(guān)頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
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