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C
OUT +
1
L
OUT
( K
2p
CO
) 2
(15)
I
COUT(RMS) +
1
12
V
OUT
V
IN(MAX) *
V
OUT
V
IN(MAX)
L
OUT
F
SW
N
C
(16)
ESR
MAX +
N
C
V
IN(MAX)
L
OUT
F
SW
0.8
V
OUT
V
IN(MAX) *
V
OUT
DVp*p(MAX)
(17)
COMPENSATION COMPONENTS
LC +
1
2p
L
OUT
C
OUT
(18)
TPS54350-EP
SGLS308 – OCTOBER 2005
Where K is the frequency multiplier for the spread between fLC and fCO. K should be between 5 and 15, typically
10 for one decade difference. For a desired crossover of 50 kHz and a 10-H inductor, the minimum value for
the output capacitor is 100 F. The selected output capacitor must be rated for a voltage greater than the desired
output voltage plus one half the ripple voltage. Any derating amount must also be included. The maximum RMS
ripple current in the output capacitor is given by Equation 16:
where NC is the number of output capacitors in parallel.
The maximum ESR of the output capacitor is determined by the amount of allowable output ripple as specified in
the initial design parameters. The output ripple voltage is the inductor ripple current times the ESR of the output
filter so the maximum specified ESR as listed in the capacitor data sheet is given by Equation 17:
Where
V
p-p is the desired peak-to-peak output ripple. For this design example, a single 100-F output capacitor
is chosen for C2 since the design goal is small size. The calculated RMS ripple current is 156 mV and the
maximum ESR required is 59 m
. A capacitor that meets these requirements is a Sanyo Poscap 6TPC100M,
rated at 6.3 V with a maximum ESR of 45 m
and a ripple current rating of 1.7 A. An additional small 0.1-F
ceramic bypass capacitor is also used.
Other capacitor types work well with the TPS54350, depending on the needs of the application.
The external compensation used with the TPS54350 allows for a wide range of output filter configurations. A
large range of capacitor values and types of dielectric are supported. The design example uses type 3
compensation consisting of R1, R3, R5, C6, C7, and C8. Additionally, R2 along with R1 forms a voltage divider
network that sets the output voltage. These component reference designators are the same as those used in the
SWIFT Designer Software. There are a number of different ways to design a compensation network. This
procedure outlines a relatively simple procedure that produces good results with most output filter combinations.
Use of the SWIFT Designer Software for designs with unusually high closed loop crossover frequencies, low
value, low ESR output capacitors such as ceramics or if the designer is unsure about the design procedure is
recommended.
When designing compensation networks for the TPS54350, a number of factors need to be considered. The gain
of the compensated error amplifier should not be limited by the open loop amplifier gain characteristics and
should not produce excessive gain at the switching frequency. Also, the closed loop crossover frequency should
be set less than one fifth of the switching frequency, and the phase margin at crossover must be greater than 45
degrees. The general procedure outlined here produces results consistent with these requirements without going
into great detail about the theory of loop compensation.
First calculate the output filter LC corner frequency using Equation 18:
For the design example, fLC = 5033 Hz.
21