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R5 +
1
2pC8
ESR
(30)
C7 +
1
8pR3
CO
(31)
BIA AND BOOTSTRAP CAPACITORS
LOW-SIDE FET
POWER GOOD
SNUBBER CIRCUIT
TPS54350-EP
SGLS308 – OCTOBER 2005
The final pole is placed at a frequency above the closed loop crossover frequency high enough to not cause the
phase to decrease too much at the crossover frequency while still providing enough attenuation so that there is
little or no gain at the switching frequency. The fP2 pole location for this circuit is set to four times the closed loop
crossover frequency and the last compensation component value C7 can be derived as follows:
Note that capacitors are only available in a limited range of standard values, so the nearest standard value has
been chosen for each capacitor. The measured closed loop response for this design is shown in
Figure 5.Every TPS54350 design requires a bootstrap capacitor, C3 and a bias capacitor, C4. The bootstrap capacitor
must be 0.1 F. The bootstrap capacitor is located between the PH pins and BOOT pin. The bias capacitor is
connected between the VBIAS pin and AGND. The value should be 1 F. Both capacitors should be high quality
ceramic types with X7R or X5R grade dielectric for temperature stability. They should be placed as close to the
device connection pins as possible.
The TPS54350 is designed to operate using an external low-side FET and the LSG pin provides the gate drive
output. Connect the drain to the PH pin, the source to PGND, and the gate to LSG. The TPS54350 gate drive
circuitry is designed to accommodate most common n-channel FETs that are suitable for this application. The
SWIFT Designer Software can be used to calculate all the design parameters for low-side FET selection. There
are some simplified guidelines that can be applied that produce an acceptable solution in most designs.
The selected FET must meet the absolute maximum ratings for the application:
Drain-source voltage (VDS) must be higher than the maximum voltage at the PH pin, which is VINMAX + 0.5 V.
Gate-source voltage (VGS) must be greater than 8 V.
Drain current (ID) must be greater than 1.1 x IOUTMAX.
Drain-source on resistance (rDSON) should be as small as possible, less than 30 m is desirable. Lower
values for rDSON result in designs with higher efficiencies. It is important to note that the low-side FET on time
is typically longer than the high-side FET on time, so attention paid to low-side FET parameters can make a
marked improvement in overall efficiency.
Total gate charge (Qg) must be less than 50 nC. Again, lower Qg characteristics result in higher efficiencies.
Additionally, check that the device chosen is capable of dissipating the power losses.
For this design, a Fairchild FDR6674A 30-V n-channel MOSFET is used as the low-side FET. This particular FET
is specifically designed to be used as a low-side synchronous rectifier.
The TPS54350 is provided with a power good output pin PWRGD. This output is an open drain output and is
intended to be pulled up to a 3.3-V or 5-V logic supply. A 10-k
, pullup resistor works well in this application. The
absolute maximum voltage is 6 V, so care must be taken not to connect this pullup resistor to VIN if the
maximum input voltage exceeds 6 V.
R4 and C11 of the application schematic in
Figure 24 comprise a snubber circuit. The snubber is included to
reduce over-shoot and ringing on the phase node when the internal high-side FET turns on. Since the frequency
and amplitude of the ringing depends to a large degree on parasitic effects, it is best to choose these component
values based on actual measurements of any design layout. See literature number
SLUP100 for more detailed
information on snubber design.
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