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參數(shù)資料
| 型號： | TPS54615MPWPREP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 12 A SWITCHING REGULATOR, 700 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | PLASTIC, HTSSOP-28 |
| 文件頁數(shù)： | 4/21頁 |
| 文件大小： | 650K |
| 代理商： | TPS54615MPWPREP |
www.ti.com
DETAILED DESCRIPTION
Under Voltage Lock Out (UVLO)
Slow-Start/Enable (SS/ENA)
t
d +
C
(SS)
1.2 V
5 mA
(2)
t
(SS) +
C
(SS)
0.7 V
5 mA
(3)
VBIAS Regulator
TPS54611-EP, TPS54612-EP
TPS54613-EP, TPS54614-EP
TPS54615-EP, TPS54616-EP
SGLS293A – FEBRUARY 2005 – REVISED AUGUST 2005
The TPS5461x incorporates an under voltage lockout circuit to keep the device disabled when the input voltage
(VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO
threshold voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins. The device
operates until VIN falls below the nominal UVLO stop threshold of 2.8 V. Hysteresis in the UVLO comparator and
a 2.5-s rising and falling edge deglitch circuit reduces the likelihood of shutting the device down due to noise on
VIN.
The slow-start/enable pin provides two functions. First, the pin acts as an enable (shutdown) control by keeping
the device turned off until the voltage exceeds the start threshold voltage of approximately 1.2 V. When SS/ENA
exceeds the enable threshold, device start up begins. The reference voltage fed to the error amplifier is linearly
ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the converter output voltage reaches regulation in
approximately 3.35 ms. Voltage hysteresis and a 2.5-s falling edge deglitch circuit reduces the chance of
triggering the enable due to noise. See the Table 1 for startup times for each device.
Table 1. Startup Times for the Devices
DEVICE
OUTPUT VOLTAGE
SLOW-START
TPS54611
0.9 V
3.3 ms
TPS54612
1.2 V
4.5 ms
TPS54613
1.5 V
5.6 ms
TPS54614
1.8 V
3.3 ms
TPS54615
2.5 V
4.7 ms
TPS54616
3.3 V
6.1 ms
The second function of the SS/ENA pin provides an external means for extending the slow-start time with a
ceramic capacitor connected between SS/ENA and AGND. Adding a capacitor to the SS/ENA pin has two effects
on start-up. First, a delay occurs between release of the SS/ENA pin and start-up of the output. The delay is
proportional to the slow-start capacitor value and lasts until the SS/ENA pin reaches the enable threshold. The
start-up delay is approximately:
Second, as the output becomes active, a brief ramp up at the internal slow-start rate may be observed before the
externally set slow-start rate takes control and the output rises at a rate proportional to the slow-start capacitor.
The slow-start time set by the capacitor is approximately:
The actual slow-start time is likely to be less than the above approximation due to the brief ramp up at the
internal rate.
The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high quality, low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are recommended because their values are more stable over
temperature. The bypass capacitor should be placed close to the VBIAS pin and returned to AGND.
External loading on VBIAS is allowed, with the caution that internal circuits require a minimum VBIAS of 2.7 V,
and external loads on VBIAS with ac or digital switching noise may degrade performance. The VBIAS pin may be
useful as a reference voltage for external circuits.
12
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