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參數資料
| 型號： | TPS54623RHLT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩壓器 |
| 英文描述： | 15 A SWITCHING REGULATOR, 1760 kHz SWITCHING FREQ-MAX, PQCC14 |
| 封裝： | 3.50 X 3.50 MM, GREEN, PLASTIC, QFN-14 |
| 文件頁數： | 17/35頁 |
| 文件大小： | 1468K |
| 代理商： | TPS54623RHLT |
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(
)
(
)
( )
m
×
=
Tss ms Iss
A
C6(nF)
Vref V
×
=
-
R5 Vref
R6
Vo
Vref
(
)
(
)
(
)
Voutmin
Ontimemin Fsmax Vinmax
Ioutmin RDS2min
RDS1min
Ioutmin RL
RDS2min
=
×
+
-
+
SLVSB09
– SEPTEMBER 2011
voltage rail to sag. Limiting the output voltage slew rate solves both of these problems. The soft start capacitor
value can be calculated using Equation 28. For the example circuit, the soft start time is not too critical since the
output capacitor value is 100
μF which does not require much current to charge to 3.3 V. The example circuit has
the soft start time set to an arbitrary value of 6 ms which requires a 22 nF capacitor. In TPS54623, Iss is 2.3 uA
and Vref is 0.6V.
(28)
Bootstrap Capacitor Selection
A 0.1
F ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10V or
higher voltage rating.
Under Voltage Lockout Set Point
The Under Voltage Lock Out (UVLO) can be adjusted using the external voltage divider network of R3 and R4.
R3 is connected between VIN and the EN pin of the TPS54623 and R4 is connected between EN and GND .
The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or
brown outs when the input voltage is falling. For the example design, the supply should turn on and start
switching once the input voltage increases above 6.528V (UVLO start or enable). After the regulator starts
switching, it should continue to do so until the input voltage falls below 6.190 V (UVLO stop or disable).
Equation 2 and Equation 3 can be used to calculate the values for the upper and lower resistor values. For the
stop voltages specified the nearest standard resistor value for R3 is 35.7 k
and for R4 is 8.06 k.
Output Voltage Feedback Resistor Selection
The resistor divider network R5 and R6 is used to set the output voltage. For the example design, 10 k
Ω was
selected for R5. Using Equation 29, R6 is calculated as 2.22 k
Ω. The nearest standard 1% resistor is 2.21 kΩ.
(29)
Minimum Output Voltage
Due to the internal design of the TPS54623, there is a minimum output voltage limit for any given input voltage.
The output voltage can never be lower than the internal voltage reference of 0.8 V. Above 0.8 V, the output
voltage may be limited by the minimum controllable on time. The minimum output voltage in this case is given by
Where:
Voutmin = minimum achievable output voltage
Ontimemin = minimum controllable on-time (135 nsec maximum)
Fsmax = maximum switching frequency including tolerance
Vinmax = maximum input voltage
Ioutmin = minimum load current
RDS1min = minimum high side MOSFET on resistance (36-32 m
typical)
RDS2min = minimum low side MOSFET on resistance (19 m
typical)
RL = series resistance of output inductor
(30)
Compensation Component Selection
There are several industry techniques used to compensate DC/DC regulators. The method presented here is
easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between
60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to
the TPS54623. Since the slope compensation is ignored, the actual cross over frequency is usually lower than
the cross over frequency used in the calculations. Use SwitcherPro software for a more accurate design.
First, the modulator pole, fpmod, and the esr zero, fzmod must be calculated using Equation 31 and Equation 32.
24
Copyright
2011, Texas Instruments Incorporated
Product Folder Link(s) :TPS54623
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