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參數資料
| 型號： | TPS54673PWP |
| 英文描述： | SMPS Controller |
| 中文描述： | 開關電源控制器 |
| 文件頁數： | 2/16頁 |
| 文件大小： | 260K |
| 代理商： | TPS54673PWP |
TPS54611, TPS54612, TPS54613
TPS54614, TPS54615, TPS54616
SLVS400A
–
AUGUST 2001
–
REVISED JANUARY 2002
2
www.ti.com
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AGND
VSENSE
NC
PWRGD
BOOT
PH
PH
PH
PH
PH
PH
PH
PH
PH
RT
FSEL
SS/ENA
VBIAS
VIN
VIN
VIN
VIN
VIN
PGND
PGND
PGND
PGND
PGND
PWP PACKAGE
(TOP VIEW)
THERMAL
PAD
AVAILABLE OPTIONS
OUTPUT
VOLTAGE
PACKAGED DEVICES
PLASTIC HTSSOP
(PWP)
OUTPUT
VOLTAGE
PACKAGED DEVICES
PLASTIC HTSSOP
(PWP)
TA
TA
0.9 V
TPS54611PWP
1.8 V
TPS54614PWP
–
40 C to 85 C
1.2 V
TPS54612PWP
–
40 C to 85 C
2.5 V
TPS54615PWP
1.5 V
TPS54613PWP
3.3 V
TPS54616PWP
The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54616PWPR).
See application section of data sheet for PowerPAD drawing and layout information.
Terminal Functions
TERMINAL
DESCRIPTION
NAME
AGND
NO.
1
Analog ground. Return for slow-start capacitor, VBIAS capacitor, RT resistor FSEL. Make PowerPAD connection to
AGND.
BOOT
5
Bootstrap input. 0.022-
μ
F to 0.1-
μ
F low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-set FET driver.
NC
3
No connection
PGND
15
–
19
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas
to the input and output supply returns, and negative terminals of the input and output capacitors.
PH
6
–
14
Phase input/output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
Power good open drain output. High-Z when VSENSE
≥
90% Vref, otherwise PWRGD is low. Note that output is low when
SS/ENA is low or internal shutdown signal active.
PWRGD
4
RT
28
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency.
SS/ENA
26
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
capacitor input to externally set the start-up time.
FSEL
27
Frequency select input. Provides logic input to select between two internally set switching frequencies.
VBIAS
25
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high
quality, low-ESR 0.1-
μ
F to 1-
μ
F ceramic capacitor.
VIN
20
–
24
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device
package with a high quality, low-ESR 1-
μ
F to 10-
μ
F ceramic capacitor.
VSENSE
2
Error amplifier inverting input. Connect directly to output voltage sense point.
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