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參數資料
| 型號： | TPS54974PWPR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩壓器 |
| 英文描述： | 16 A SWITCHING REGULATOR, 762 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | GREEN, PLASTIC, HTSSOP-28 |
| 文件頁數： | 21/21頁 |
| 文件大小： | 743K |
| 代理商： | TPS54974PWPR |
www.ti.com
V
O(max) +
PVIN
(min)
0.9
(2)
PCB LAYOUT
-
+
PVIN
VBIAS
SS/ENA
10 k
10 k
27.4 k
100 k
VIN
1/2 LM293
OUTPUT FILTER
MAXIMUM OUTPUT VOLTAGE
TPS54974
SLVS458B – JANUARY 2003 – REVISED FEBRUARY 2005
PVIN input connected to a separate power source
from VIN. The primary intended application has VIN
connected to a 3.3-V bus and PVIN connected to a
Care must be taken while operating when nominal
2.5-V bus. The TPS54974 cannot be damaged by
conditions cause duty cycles near 90%. Load transi-
any sequencing of these voltages. However, the
ents can require momentary increases in duty cycle.
UVLO (see detailed description section) is referenced
If the required duty cycle exceeds 90%, the output
to the VIN input. Some conditions may cause unde-
may fall out of regulation.
sirable operation.
If PVIN is absent when the VIN input is high, the
slow-start is released, and the PWM circuit goes to
Figure 12 shows a generalized PCB layout guide for
maximum duty factor. When the PVN input ramps up,
the TPS54974.
the output of the TPS54974 follows the PVIN input
The PVIN pins should be connected together on the
until enough voltage is present to regulate to the
printed-circuit board (PCB) and bypassed with a
proper output value.
low-ESR ceramic bypass capacitor. Care should be
taken to minimize the loop area formed by the bypass
NOTE:
capacitor
connections,
the
VIN
pins,
and
the
TPS54974 ground pins. The minimum recommended
If the PVIN input is controlled via a fast bus switch, it
bypass capacitance is 10 F ceramic with a X5R or
results in a hard-start condition and may damage the
X7R dielectric and the optimum placement is closest
load (i.e., whatever is connected to the regulated
to the VIN pins and the PGND pins. If the VIN is
output of the TPS54974). If a power-good signal is
connected to a separate source supply, it should be
not available from the 2.5-V power supply, one can
bypassed with its own capacitor.
be generated using a comparator and hold the
SS/ENA pin low until the 2.5-V bus power is good. An
The TPS54974 has two internal grounds (analog and
example of this is shown in Figure 11. This circuit can
power). Inside the TPS54974, the analog ground ties
also be used to prevent the TPS54974 output from
to all of the noise-sensitive signals, while the power
following the PVIN input while the PVIN power supply
ground ties to the noisier power signals. Noise
is ramping up.
injected between the two grounds can degrade the
performance of the TPS54974, particularly at higher
output currents. Ground noise on an analog ground
plane can also cause problems with some of the
control and bias signals. For these reasons, separate
analog and power ground traces are recommended.
There should be an area of ground on the top layer
directly under the IC, with an exposed area for
connection to the PowerPAD. Use vias to connect
Figure 11. Undervoltage Lockout Circuit for PVIN
this ground area to any internal ground planes. Use
Using Open-Collector or Open-Drain Comparator
additional vias at the ground side of the input and
output filter capacitors as well. The AGND and PGND
PVIN and VIN can be tied together for 3.3-V bus
pins should be tied to the PCB ground by connecting
operation.
them to the ground area under the device as shown.
The only components that should tie directly to the
power ground plane are the input capacitors, the
output capacitors, the input voltage decoupling ca-
The output filter is composed of a 0.65-H inductor
pacitor, and the PGND pins of the TPS54974. Use a
and 3 x 22-F capacitor. The inductor is a low
separate wide trace for the analog ground signal
dc-resistance (0.017
) type, Pulse Engineering
path. This analog ground should be used for the
PA0277. The capacitors used are 22-F, 6.3-V cer-
voltage set-point divider, timing resistor RT, slow-start
amic types with X5R dielectric. The feedback loop is
capacitor, and bias-capacitor grounds. Connect this
compensated so that the unity gain frequency is
trace directly to AGND (pin 1).
approximately 75 kHz.
The PH pins should be tied together and routed to
the output inductor. Because the PH connection is
the switching node, the inductor should be located
The maximum attainable output voltage is limited by
close to the PH pins and the area of the PCB
the minimum voltage at the PVIN pin. Nominal
conductor minimized to prevent excessive capacitive
maximum duty cycle is limited to 90% in the
coupling.
TPS54974, so maximum output voltage is:
9
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| TPS54980PWP | 功能描述:直流/直流開關調節器 3.3V Inp Sync Buck Converter RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數量: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
| TPS54980PWPG4 | 功能描述:直流/直流開關調節器 3.3V Input Synch Buck Converter RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數量: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
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