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參數資料
| 型號： | TPS54974PWPR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩壓器 |
| 英文描述： | 16 A SWITCHING REGULATOR, 762 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | GREEN, PLASTIC, HTSSOP-28 |
| 文件頁數： | 4/21頁 |
| 文件大小： | 743K |
| 代理商： | TPS54974PWPR |
www.ti.com
2
V/div
5 ms/div
Vout = 1.8 V
SS/ENA
Non Inverting Comparator Input
2
V/div
2
V/div
1
V/div
Vin
50
mV/div
1
s/div
Vphase
2
A/div
Vout
50
mV/div
500
s/div
Iout = 2.25 to 6.75 A Step
DETAILED DESCRIPTION
UNDERVOLTAGE LOCKOUT (UVLO)
t
d +
C
(SS)
1.2 V
5 mA
(3)
SLOW-START/ENABLE (SS/ENA)
t
(SS) +
C
(SS)
0.7 V
5 mA
(4)
VBIAS REGULATOR (VBIAS)
TPS54974
SLVS458B – JANUARY 2003 – REVISED FEBRUARY 2005
PERFORMANCE GRAPHS (continued)
INPUT RIPPLE VOLTAGE
LOAD TRANSIENT RESPONSEDummy
START UP WAVEFORM(2)
Figure 19.
Figure 20.
Figure 21.
1. Safe operating area is applicable to the test board conditions in the Dissipation Ratings.
2. Using the undervoltage lockout circuit of Figure 11.
Adding a capacitor to the SS/ENA pin has two effects
on start-up. First, a delay occurs between release of
the SS/ENA pin and start-up of the output. The delay
The TPS54974 incorporates an undervoltage lockout
is proportional to the slow-start capacitor value and
circuit to keep the device disabled when the input
lasts until the SS/ENA pin reaches the enable
voltage (VIN) is insufficient. During power up, internal
threshold. The start-up delay is approximately:
circuits are held inactive until VIN exceeds the
nominal UVLO threshold voltage of 2.95 V. Once the
UVLO start threshold is reached, device start-up
begins. The device operates until VIN falls below the
nominal UVLO stop threshold of 2.8 V. Hysteresis in
Second, as the output becomes active, a brief
the UVLO comparator, and a 2.5-s rising and falling
ramp-up at the internal slow-start rate may be ob-
edge deglitch circuit reduce the likelihood of shutting
served before the externally set slow-start rate takes
the device down due to noise on VIN. The UVLO is
control and the output rises at a rate proportional to
with respect to VIN and not PVIN; see application
the slow-start capacitor. The slow-start time set by
note.
the capacitor is approximately:
The slow-start/enable pin provides two functions.
The actual slow-start time is likely to be less than the
First, the pin acts as an enable (shutdown) control by
above approximation due to the brief ramp-up at the
keeping the device turned off until the voltage ex-
internal rate.
ceeds the start threshold voltage of approximately 1.2
V. When SS/ENA exceeds the enable threshold,
device start-up begins. The reference voltage fed to
the error amplifier is linearly ramped up from 0 V to
The VBIAS regulator provides internal analog and
0.891 V in 3.35 ms. Similarly, the converter output
digital blocks with a stable supply voltage over
voltage reaches regulation in approximately 3.35 ms.
variations in junction temperature and input voltage. A
Voltage hysteresis and a 2.5-s falling edge deglitch
high quality, low-ESR, ceramic bypass capacitor is
circuit reduce the likelihood of triggering the enable
required on the VBIAS pin. X7R- or X5R-grade
due to noise.
dielectrics are recommended because their values
are more stable over temperature. The bypass ca-
The second function of the SS/ENA pin provides an
pacitor must be placed close to the VBIAS pin and
external means of extending the slow-start time with
returned to AGND.
a low-value capacitor connected between SS/ENA
and AGND.
External loading on VBIAS is allowed, with the
caution that internal circuits require a minimum
12
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