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參數(shù)資料
| 型號(hào)： | TPS5615CPWP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, PDSO28 |
| 封裝： | PLASTIC, TSSOP-28 |
| 文件頁數(shù)： | 19/25頁 |
| 文件大?。?/td> | 387K |
| 代理商： | TPS5615CPWP |
TPS5615, TPS5618, TPS5625, TPS5633
SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER
SLVS177A – SEPTEMBER 1998 – REVISED NOVEMBER 1998
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AGND2
2
Analog ground (must be connected).
ANAGND
7
Analog ground
BIAS
9
Analog bias pin. A 1-
F capacitor should be connected from BIAS to ANAGND.
BOOT
16
Bootstrap. A 1-
F capacitor should be connected from BOOT to BOOTLO.
BOOTLO
18
Bootstrap low. Connect to the junction of the high-side and low-side FETs for floating drive configuration.
Connect to PGND for ground-reference drive configuration.
DRV
14
Drive regulator for the FET drivers. A 1-
F capacitor should be connected from DRV to DRVGND.
DRVGND
12
Drive ground. Ground for FET drivers. Connect to FET PWRGND.
HIGHDR
17
High drive. Output drive to high-side power switching FETs.
HISENSE
19
High current sense. For current sensing across high-side FETs, connect to the drain of the high-side FETs;
for optional current sensing scheme, connect to power supply side of current-sense resistor placed in series
with high-side FET drain.
INHIBIT
22
Disables the drive signals to the MOSFET drivers. Also serves as UVLO for system logic supply (3.3 V or
5 V). An external pull-up resistor should be connected to system-logic supply.
IOUT
1
Current out. Output voltage on this terminal is proportional to the load current as measured across the
Rds(on) of the high side FET. The voltage on this terminal equals 2 × RDS(ON) × IOUT. In applications where
very accurate current-sensing is required, a sense resistor should be connected between the input supply
and the drain of the high-side FETs.
IOUTLO
21
Current sense low output. This is the voltage on the LOSENSE terminal when the high-side FETs are on.
A ceramic capacitor (between 0.033
F and 0.1 F) should be connected from IOUTLO to HISENSE to hold
the sensed voltage.
LODRV
10
Low drive enable. Normally tied to 5 V. To configure the low-side FET as a crowbar, pull LODRV low.
LOHIB
11
Low side inhibit. Connect to the junction of the high- and low-side FETs to control the anti-cross-
conduction and eliminate shoot-through current. Disabled when configured in crowbar mode.
LOSENSE
20
Low current sense. For current sensing across high-side FETs, connect to the source of the high-side FETs;
for optional current sensing scheme, connect to high-side FET drain side of current-sense resistor placed
in series with high-side FET drain.
LOWDR
13
Low drive. Output drive to synchronous rectifier FETs.
NC
23–27
No connect
OCP
3
Over current protection. Current limit trip point is set with a resistor divider between IOUT and ANAGND.
PWRGD
28
Power good. PWRGD signal goes high when output voltage is within 7% of voltage setpoint. Open-drain
output.
SLOWST
8
Slow Start (soft start). A capacitor form SLOWST to ANAGND sets the slowstart time.
Slowstart current = IVREFB/5
VHYST
4
Hysteresis set input. The hysteresis is set with a resistor divider from VREFB to ANAGND.
Hysteresis = 2
× (VREFB – VHYST)
VCC
15
12-V supply. A 1-
F capacitor should be connected from VCC to DRVGND.
VREFB
5
Buffered reference voltage
VSENSE
6
Voltage sense Input. To be connected from converter output voltage bus to sense and control output voltage.
It is recommended that a RC low-pass filter be connected at this pin to filter noise.
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