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參數資料
| 型號： | TPS61251DSG |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩壓器 |
| 英文描述： | SWITCHING REGULATOR, 3500 kHz SWITCHING FREQ-MAX, PDSO8 |
| 封裝： | 2 X 2 MM, PLASTIC, WSON-8 |
| 文件頁數： | 7/21頁 |
| 文件大小： | 446K |
| 代理商： | TPS61251DSG |
www.ti.com
SLVSAF7 – SEPTEMBER 2010
INPUT CAPACITOR
Multilayer ceramic capacitors are an excellent choice for input decoupling of the step-up converter as they have
extremely low ESR and are available in small form factors. Input capacitors should be located as close as
possible to the device. While a 10mF input capacitor is sufficient for most applications, larger values may be used
to reduce input current ripple on the supply rail without limitations. Although low ESR tantalum capacitors may be
used.
NOTE
DC Bias effect: High capacitance ceramic capacitors have a DC Bias effect, which will
have a strong influence on the final effective capacitance. Therefore the right capacitor
value has to be chosen very carefully. Package size and voltage rating in combination with
material are responsible for differences between the rated capacitor value and the
effective capacitance. A 10 V rated 0805 capacitor with 10 F can have an effective
capacitance of less 5 F at an output voltage of 5 V.
CHECKING LOOP STABILITY
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:
Switching node, SW
Inductor current, IL
Output ripple voltage, VOUT(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between
the load transient takes place and the turn on of the PMOS switch, the output capacitor must supply all of the
current required by the load. VOUT immediately shifts by an amount equal to ΔI(LOAD) x ESR, where ESR is the
effective series resistance of COUT. ΔI(LOAD) begins to charge or discharge COUT generating a feedback error
signal used by the regulator to return VOUT to its steady-state value. The results are most easily interpreted when
the device operates in PWM mode.
During this recovery time, VOUT can be monitored for settling time, overshoot or ringing that helps judge the
converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin. Because the
damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET rDS(on)) that are
temperature dependant, the loop stability analysis has to be done over the input voltage range, load current
range, and temperature range.
LAYOUT CONSIDERATIONS
For all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC.
Use a common ground node for power ground and a different one for control ground to minimize the effects of
ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC.
The feedback divider should be placed close to the IC to keep the feedback connection short. To lay out the
ground, short traces and wide are recommended. This avoids ground shift problems, which can occur due to
superimposition of power ground current and the feedback divider.
Copyright 2010, Texas Instruments Incorporated
15
Product Folder Link(s): TPS61251
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