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參數資料
| 型號： | TPS65058RGET |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩壓器 |
| 英文描述： | 1.8 A DUAL SWITCHING CONTROLLER, 2475 kHz SWITCHING FREQ-MAX, PQCC32 |
| 封裝： | 4 X 4 MM, GREEN, PLASTIC, VQFN-32 |
| 文件頁數： | 7/26頁 |
| 文件大小： | 1898K |
| 代理商： | TPS65058RGET |
100% Duty Cycle Low Dropout Operation
Undervoltage Lockout
MODE SELECTION
ENABLE
OUTPUT VOLTAGE SELECTION
www.ti.com................................................................................................................................................... SLVS851A – MAY 2008 – REVISED SEPTEMBER 2008
The converters offer a low input to output voltage difference while still maintaining operation with the use of the
100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly useful in
battery-powered applications to achieve longest operation time by taking full advantage of the whole battery
voltage range, i.e. The minimum input voltage to maintain regulation depends on the load current and output
voltage and can be calculated as:
VImin = VOUTmax + IOUTmax × (RDS(on)max + RL)
with:
IOUTmax = maximum output current plus inductor ripple current
RDS(on)max = maximum P-channel switch rDS(on)
RL = DC resistance of the inductor
VOUTmax = nominal output voltage plus maximum output voltage tolerance
With decreasing load current, the device automatically switches into pulse skipping operation in which the power
stage operates intermittently based on load demand. By running cycles periodically the switching losses are
minimized and the device runs with a minimum quiescent current maintaining high efficiency.
In power save mode, the converter only operates when the output voltage trips below its nominal output voltage.
It ramps up the output voltage with several pulses and goes again into power save mode once the output voltage
exceeds the nominal output voltage.
The undervoltage lockout circuit prevents the device from malfunctioning by disabling the converter at low input
voltages and from excessive discharge of the battery. The undervoltage lockout threshold is typically 1.8 V, max
2 V.
The MODE pin allows mode selection between forced PWM Mode and power Save Mode for both converters.
Connecting this pin to GND enables the automatic PWM and power save mode operation. The converters
operate in fixed frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads,
maintaining high efficiency over a wide load current range.
Pulling the MODE pin high forces both converters to operate constantly in the PWM mode even at light load
currents. The advantage is the converters operate with a fixed frequency that allows simple filtering of the
switching frequency for noise sensitive applications. In this mode, the efficiency is lower compared to the power
save mode during light loads. For additional flexibility it is possible to switch from power save mode to forced
PWM mode during operation. This allows efficient power management by adjusting the operation of the converter
to the specific system requirements.
The device has a separate enable pin for each dcdc converter and for each LDO to start up each converter
independently. If EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, EN_LDO3 are set to high, the corresponding
converter starts up with soft start as previously described.
Pulling the enable pin low forces the device into shutdown, with a shutdown quiescent current as defined in the
electrical characteristics. In this mode, the P and N-Channel MOSFETs are turned-off, the and the entire internal
control circuitry is switched-off. If disabled, the outputs of the LDOs are pulled low by internal 300
resistors,
actively discharging the output capacitor. For proper operation, the enable pins must be terminated and must not
be left unconnected.
The output voltage of the DCDC Converter 2 can be selected by a logic level on pin DEF_DCDC2. The output
voltage can be changed dynamically during operation. The slew rate of the change of output voltage is controlled
on DCDC2 to be 9.6mV/
s.
The output voltages on the LDOs can also be changed dynamically between two voltages by changing the logic
level on pin DEF_LDO.
Copyright 2008, Texas Instruments Incorporated
15
Product Folder Link(s) :TPS65058
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