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參數資料
| 型號： | TPS65910RSLT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PQCC48 |
| 封裝： | 6 X 6 MM, 0.40 MM PITCH, GREEN, PLASTIC, VQFN-48 |
| 文件頁數： | 69/86頁 |
| 文件大小： | 534K |
| 代理商： | TPS65910RSLT |
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SWCS046A – MARCH 2010 – REVISED MAY 2010
Bits
Field Name
Description
Type
Reset
1
DEV_SLP
Write 1 allows SLEEP device state (if DEV_OFF = 0 and
RW
0
DEV_OFF_RST = 0).
Write ‘0’ will start an SLEEP to ACTIVE device state transition (wake-up
event) (if DEV_OFF = 0 and DEV_OFF_RST = 0). This bit is cleared in
OFF state.
0
DEV_OFF
Write 1 will start an ACTIVE to OFF or SLEEP to OFF device state
RW
0
transition (switch-off event). This bit is cleared in OFF state.
Table 59. DEVCTRL2_REG
Address Offset
0x40
Physical Address
Instance
Description
Device control register
Type
RW
7
6
5
4
3
2
1
0
Reserved
TSLOT_LENGTH
IT_POL
PWON_LP_OFF
PWON_LP_RST
SLEEPSIG_POL
Bits
Field Name
Description
Type
Reset
7:6
Reserved
Reserved bit
RO
0x0
R returns
0s
5:4
TSLOT_LENGTH
Time slot duration programming (EEPROM bit):
RW
0x3
When 00 : 0 s
When 01 : 200 s
When 10 : 500 s
When 11 : 2 ms
3
SLEEPSIG_POL
When 1, SLEEP signal active high
RW
0
When 0, SLEEP signal active low
2
PWON_LP_OFF
When 1, allows device turn-off after a PWON Long Press (signal low).
RW
1
PWON_LP_RST
When 1, allows digital core reset when the device is OFF.
RW
0
IT_POL
INT1 interrupt pad polarity control signal (EEPROM bit):
RW
0
When 0, active low
When 1, active high
Table 60. SLEEP_KEEP_LDO_ON_REG
Address Offset
0x41
Physical Address
Instance
Description
When corresponding control bit=0 in EN1/2_ LDO_ASS register (default setting): Configuration Register
keeping the full load capability of LDO regulator (ACTIVE mode) during the SLEEP state of the device.
When control bit=1, LDO regulator full load capability (ACTIVE mode) is maintained during device
SLEEP state.
When control bit=0, the LDO regulator is set or stay in low power mode during device SLEEP state(but
then supply state can be overwritten programming ST[1:0]). Control bit value has no effect if the LDO
regulator is off.
When corresponding control bit=1 in EN1/2_ LDO_ASS register: Configuration Register setting the LDO
regulator state driven by SCLSR_EN1/2 signal low level (when SCLSR_EN1/2 is high the regulator is
on, full power):
- the regulator is set off if its corresponding Control bit = 0 in SLEEP_KEEP_LDO_ON register (default)
- the regulator is set in low power mode if its corresponding control bit = 1 in SLEEP_KEEP_LDO_ON
register
Type
RW
Copyright 2010, Texas Instruments Incorporated
71
Product Folder Link(s): TPS65910
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