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| 型號： | TPS65910RSLT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PQCC48 |
| 封裝： | 6 X 6 MM, 0.40 MM PITCH, GREEN, PLASTIC, VQFN-48 |
| 文件頁數(shù)： | 74/86頁 |
| 文件大小： | 534K |
| 代理商： | TPS65910RSLT |
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PRODUCTPREVIEW
SWCS046A – MARCH 2010 – REVISED MAY 2010
www.ti.com
Bits
Field Name
Description
Type
Reset
0
VIO_EN1
When control bit = 1, supply state is driven by the SCLSR_EN1 control
RW
0
signal and is also defined though SLEEP_KEEP_RES_ON register
setting:
When SCLSR_EN1 is high the supply is on,
When SCLSR_EN1 is low:
- the supply is off (default) or the SMPS is working in low power mode if
VIO_KEEPON = 1
When control bit = 0 no effect: SMPS state is driven though registers
programming and the device state
Table 66. EN2_LDO_ASS_REG
Address Offset
0x47
Physical Address
Instance
Description
Configuration Register setting the LDO regulators, driven by the multiplexed SDASR_EN2 signal.
When control bit = 1, LDO regulator state is driven by the SDASR_EN2 control signal and is also
defined though SLEEP_KEEP_LDO_ON register setting:
When SDASR_EN2 is high the regulator is on,
When SCLSR_EN2 is low:
- the regulator is off if its corresponding Control bit = 0 in SLEEP_KEEP_LDO_ON register
- the regulator is working in low power mode if its corresponding control bit = 1 in
SLEEP_KEEP_LDO_ON register
When control bit = 0 no effect: LDO regulator state is driven though registers programming and the
device state
Any control bit of this register set to 1 will disable the I2C SR Interface functionality
Type
RW
7
6
5
4
3
2
1
0
VDAC_EN2
VPLL_EN2
VAUX33_EN2
VAUX2_EN2
VAUX1_EN2
VDIG2_EN2
VDIG1_EN2
VMMC_EN2
Bits
Field Name
Description
Type
Reset
7
VDAC_EN2
Setting supply state control though SDASR_EN2 signal
RW
0
6
VPLL_EN2
Setting supply state control though SDASR_EN2 signal
RW
0
5
VAUX33_EN2
Setting supply state control though SDASR_EN2 signal
RW
0
4
VAUX2_EN2
Setting supply state control though SDASR_EN2 signal
RW
0
3
VAUX1_EN2
Setting supply state control though SDASR_EN2 signal
RW
0
2
VDIG2_EN2
Setting supply state control though SDASR_EN2 signal
RW
0
1
VDIG1_EN2
Setting supply state control though SDASR_EN2 signal
RW
0
VMMC_EN2
Setting supply state control though SDASR_EN2 signal
RW
0
Table 67. EN2_SMPS_ASS_REG
Address Offset
0x48
Physical Address
Instance
Description
Configuration Register setting the SMPS Supplies driven by the multiplexed SDASR_EN2 signal.
When control bit = 1, SMPS Supply state and voltage is driven by the SDASR_EN2 control signal and is
also defined though SLEEP_KEEP_RES_ON register setting.
When control bit = 0 no effect: SMPS Supply state is driven though registers programming and the
device state
Any control bit of this register set to 1 will disable the I2C SR Interface functionality
Type
RW
7
6
5
4
3
2
1
0
RSVD
SPARE_EN2
VDD3_EN2
VDD2_EN2
VDD1_EN2
VIO_EN2
76
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS65910
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