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參數資料
| 型號： | TPS65930A2ZCH |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA139 |
| 封裝： | 10 X 10 MM, 0.65 MM PITCH, GREEN, PLASTIC, NFBGA-139 |
| 文件頁數： | 87/115頁 |
| 文件大小： | 1232K |
| 代理商： | TPS65930A2ZCH |
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UART_TX
DM
DP
UART_RX
CK1
CK2
CK3
CK4
037-047
SWCS037G
– MAY 2008 – REVISED APRIL 2011
Table 7-4. USB-CEA Carkit UART Timings
Notation
Parameter
Min
Max
Unit
CK1
td(UART_TXH-DM)
Delay time, UART_TX rising edge to DM transition
4.0
11
ns
CK2
td(UART_TXL-DM)
Delay time, UART_TX falling edge to DM transition
4.0
11
ns
At 38.4 MHz
205
234
Delay time, DP rising edge to UART_RX
CK3
td(DPH-UART_RX)
ns
transition
At 19.2 MHz
310
364
At 38.4 MHz
205
234
Delay time, DP falling edge to UART_RX
CK4
td(DPL-UART_RX)
ns
transition
At 19.2 MHz
310
364
Figure 7-5 shows the USB-CEA carkit UART timings.
Figure 7-5. USB-CEA Carkit UART Timings
7.1.4
PHY Electrical Characteristics
The PHY is the physical signaling layer of the USB 2.0. It contains the drivers and receivers for physical
data and protocol signaling on the DP and DM lines.
The PHY interfaces with the USB controller through the UTMI.
The transmitters and receivers in the PHY are of two main classes:
FS and LS transceivers (legacy USB1.x transceivers)
HS transceivers
To bias the transistors and run the logic, the PHY also contains reference generation circuitry which
consists of:
A DPLL that does a frequency multiplication to achieve the 480-MHz low-jitter lock necessary for USB,
and the clock required for the switched capacitor resistance block
A switched capacitor resistance block that replicates an external resistor on chip
Built-in pullup and pulldown resistors are used as part of the protocol signaling.
The PHY also contains circuitry that protects it from an accidental 5-V short on the DP and DM lines and
from 8-kV IEC ESD strikes.
7.1.4.1
HS Differential Receiver
The HS receiver consists of the following blocks:
A differential input comparator to receive the serial data
A squelch detector to qualify the received data
An oversampler-based clock data recovery scheme followed by a nonreturn to zero inverted (NRZI)
decoder, bit unstuffing, and serial-to-parallel converter to generate the UTMI DATAOUT
Table 7-5 lists the characteristics of the HS differential receiver.
Copyright
2008–2011, Texas Instruments Incorporated
USB Transceiver
73
focus.ti.com: TPS65930/TPS65920
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| TPS65930A2ZCHR | 功能描述:PMIC 解決方案 Int Pwr Mgmt IC RoHS:否 制造商:Texas Instruments 安裝風格:SMD/SMT 封裝 / 箱體:QFN-24 封裝:Reel |
| TPS65930BZCH | 功能描述:開關變換器、穩壓器與控制器 Int Pwr Mgmt IC RoHS:否 制造商:Texas Instruments 輸出電壓:1.2 V to 10 V 輸出電流:300 mA 輸出功率: 輸入電壓:3 V to 17 V 開關頻率:1 MHz 工作溫度范圍: 安裝風格:SMD/SMT 封裝 / 箱體:WSON-8 封裝:Reel |
| TPS65930BZCH | 制造商:Texas Instruments 功能描述:IC POWER MANAGEMENT ((NW)) |
| TPS65930BZCHR | 功能描述:開關變換器、穩壓器與控制器 Int Pwr Mgmt IC RoHS:否 制造商:Texas Instruments 輸出電壓:1.2 V to 10 V 輸出電流:300 mA 輸出功率: 輸入電壓:3 V to 17 V 開關頻率:1 MHz 工作溫度范圍: 安裝風格:SMD/SMT 封裝 / 箱體:WSON-8 封裝:Reel |
| TPS65950A2ZXN | 功能描述:PMIC 解決方案 Integ Pwr Mgmt IC RoHS:否 制造商:Texas Instruments 安裝風格:SMD/SMT 封裝 / 箱體:QFN-24 封裝:Reel |
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