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參數(shù)資料
| 型號： | TPU3040PQ |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | 圖文 |
| 英文描述： | TELETEXT DECODER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 62/72頁 |
| 文件大小： | 576K |
| 代理商： | TPU3040PQ |
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TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
MICRONAS INTERMETALL
65
029F H
Write
ACQ STANDARD
Bit
Reset
Function
7
0
1 = CAPTION enable in field 2
0 = CAPTION disable in field 2
6
0
1 = CAPTION enable in field 1
0 = CAPTION disable in field 1
5
0
1 = VPS enable
0 = VPS disable
7 to 5
0
VPS and CAPTION cannot be used at the same time, therefore these combinations are used to enable
WSS reception on a PAL+ signal
0 =
1 = VPS
2 = CAPTION field 1
3 = WSS & VPS
4 = CAPTION field 2
5 = WSS & VPS
6 = CAPTION field 1&2
7 = WSS
4
1
1 = TTX enable
0 = TTX disable
3
1
1 = MAC VBI channel A
0 = MAC VBI channel B
2
0
1 = MAC packet acquisition enable
0 = MAC VBI acquisition enable
1
0
1 = NTSC mode
0 = PAL mode
0
1 = MAC mode
0 = composite video mode
1 to 0
0
MAC and NTSC cannot be used at the same time, therefore this combination is used to enable full VBI data
reception in Caption mode
02A0 H
Write
ACQ ANALOG MODE
Bit
Reset
Function
7
0
1 = full N clamping
(
*150 A)
0 = half N clamping
(
* 75 A)
6
1
1 = N clamping disable
0 = N clamping enable
(
*150 A if data < sync slicer level)
5
0
1 = clamping disable
0 = clamping enable
(+225
A if data = 0, *6 A static)
4 to 0
10 H
5 bit analog gain of AGC
31 = 12dB
16 = 6dB
00 = 0dB
02A3 H
Write
ACQ VIDEO INPUT
Bit
Reset
Function
0
1 = video input 2
(pin 44)
0 = video input 1
(pin 42)
02A4 H
Read
ACQ HSYNC COUNTER
Bit
Reset
Function
7 to 0
0
number of detected horizontal sync pulses per frame divided by 4
sync pulse is detected if within horizontal window of HPLL
counter is latched with vertical sync, the register can be read at any time
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