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參數資料
| 型號： | TRIMEDIA_TM-1100 |
| 英文描述： | Programmable Media Processor |
| 中文描述： | 可編程的媒體處理器 |
| 文件頁數： | 5/8頁 |
| 文件大小： | 289K |
| 代理商： | TRIMEDIA_TM-1100 |
internal I/O requirements of its target applications, the TM-1100
couples substantial on-chip caches with a glueless memory interface.
Dedicated instruction and data cache —
TM-1100’s CPU is
supported by separate, dedicated on-chip data and instruction caches.
Even without a second-level cache structure, TriMedia caches deliver
media performance an order of magnitude greater than x86 processors.
The dual-ported data cache allows two simultaneous accesses. It is
non-blocking, thus cache misses and CPU cache accesses can be han-
dled simultaneously. Early restart techniques reduce read-miss latency.
Background copyback reduces CPU stalls.
To reduce internal bus bandwidth requirements, instructions in main
memory and cache use a compressed format. The compressed instruc-
tion format improves the cache hit rate and reduces bus bandwidth.
Instructions are compressed during compilation and decompressed in
the instruction cache before being processed by the CPU.
To improve cache behavior and thus performance, both caches have
a locking mechanism. Cache coherency is maintained by software.
Glueless memory system interface —
TM-1100’s glueless main
memory interface couples the on-chip caches and multimedia
peripheral units to main memory (SDRAM). It acts as the SDRAM
controller and programmable central arbiter that allocates SDRAM
memory bandwidth for on-chip peripheral unit activities. Higher
bandwidth SDRAM permits TM-1100 to use a narrower and simpler
interface than would be required to achieve similar performance with
standard DRAM.
The TM-1100 memory interface provides sufficient capacity to drive
a memory system consisting of up to 133-MHz, 8-MB (four 2Mx8)
or 16-MB (two 2Mx32) SDRAMs. Larger memories can be imple-
mented by using lower memory system clock frequencies or external
buffers. Programmable speed ratios allow SDRAM to have a different
clock speed than the TM-1100 CPU. Support for a variety of memory
types, speeds, bus widths, and off-chip bank sizes allow a range of
TM-1100-based systems to be configured.
HIGH-SPEED INTERNAL BUS (DATA HIGHWAY)
The memory system interface also mediates bandwidth allocation of
the TM-1100’s on-chip central data highway. A high-speed internal
bus consisting of separate 32-bit address and data buses, the data high-
way connects the CPU and all on-chip I/O and coprocessing units to
external SDRAM (through the memory interface) and to an off-chip
PCI or XIO bus (through the PCI/XIO interface). Programmable
bandwidth enables the data highway to deliver real-time responsive-
ness in a variety of multimedia applications.
RESULT
SOURCE REGISTER 1
SOURCE REGISTER 2
A
B
C
D
|A-E| + |B-F| + |C-G| + |D-H|
E
F
G
H
31
0
31
0
31
0
UME8UU:
SUM OF ABSOLUTE VALUES
OF UNSIGNED 8-BIT DIFFERENCES
DSPALU
FUNCTIONAL
UNIT
DESTINATION
REGISTER
SPECIAL MULTIMEDIA OPERATIONS
The ume8uu operation, commonly used for motion estimation in
video compression, implements 11 simple operations in one
TriMedia special op.
TM-1100 is designed for use as a coprocessor in a PC-hosted
environment or as the sole CPU in standalone systems.
HOST-ASSISTED COPROCESSOR
STANDALONE
S D R A M
AUDIO
AUDIO
CAMERA
VCR
TV MONITOR
PCI
/
XIO BUS
HOST CPU
MEMORY
GRAPHICS
CARD
RGB IMAGE SEQUENCES
S D R A M
AUDIO
AUDIO
CAMERA
VCR
TV MONITOR
PCI
/
XIO BUS
ROM/FLASH
BUS
ARBITER
PERIPHERAL
PERIPHERAL
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