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參數資料
型號: TS8308500CG
廠商: E2V TECHNOLOGIES PLC
元件分類: ADC
英文描述: 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72
封裝: 1.27 MM PITCH, HEAT SINK, CERAMIC, BGA-72
文件頁數: 20/42頁
文件大小: 641K
代理商: TS8308500CG
27
Preliminary Specification
ββββ-site
TS8308500
(TR)
Rise time
Time delay for the output DATA signals to rise from 20% to 80% of delta between low level and
high level.
(TF)
Fall time
Time delay for the output DATA signals to fall from 80% to 20% of delta between low level and
high level.
(PSRR)
Power supply
rejection ratio
Ratio of input offset variation to a change in power supply voltage.
(NRZ)
Non return to zero
When the input signal is larger than the upper bound of the ADC input range, the output code is
identical to the maximum code and the Out of Range bit is set to logic one. When the input
signal is smaller than the lower bound of the ADC input range, the output code is identical to the
minimum code, and the Out of range bit is set to logic one. (It is assumed that the input signal
amplitude remains within the absolute maximum ratings).
(IMD)
InterModulation Distortion
The two tones intermodulation distortion ( IMD ) rejection is the ratio of either input tone to the
worst third order intermodulation products. The input tones levels are at – 7dB Full Scale.
(NPR)
Noise Power Ratio
The NPR is measured to characterize the ADC performance in response to broad bandwidth
signals. When using a notch-filtered broadband white-noise generator as the input to the ADC
under test, the Noise Power Ratio is defined as the ratio of the average out-of-notch to the
average in-notch power spectral density magnitudes for the FFT spectrum of the ADC output
sample test.
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