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參數資料
| 型號： | TS8308500CG |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72 |
| 封裝： | 1.27 MM PITCH, HEAT SINK, CERAMIC, BGA-72 |
| 文件頁數： | 23/42頁 |
| 文件大小： | 641K |
| 代理商： | TS8308500CG |
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3
Preliminary Specification
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TS8308500
1.
SIMPLIFIED BLOCK DIAGRAM
2.
FUNCTIONAL DESCRIPTION
The TS8308500 is an 8 bit 500MSPS ADC based on an advanced high speed bipolar technology featuring a cutoff frequency of 25 GHz.
The TS8308500 includes a front-end master/slave Track and Hold stage (S/H), followed by an analog encoding stage and interpolation circuitry.
Successive banks of latches are regenerating the analog residues into logical data before entering an error correction circuitry and a
resynchronization stage followed by 75
differential output buffers.
The TS8308500 works in fully differential mode from analog inputs up to digital outputs.
The TS8308500 features a full power input bandwidth of 1.3 GHz.
Control pin GORB is provided to select either Gray or Binary data output format.
Gain control pin is provided in order to adjust the ADC gain.
A Data Ready output asynchronous reset (DRRB) is available on TS8308500.
The TS8308500 uses only vertical isolated NPN transistors together with oxide isolated polysilicon resistors, which allow enhanced radiation
tolerance (no performance drift measured at 150kRad total dose).
VIN,VINB
CLK, CLKB
G=2
T/H
G=1
T/H
G=1
CLOCK
BUFFER
RESISTOR
CHAIN
ANALOG
ENCODING
BLOCK
INTERPOLATION
STAGES
REGENERATION
LATCHES
ERROR CORRECTION &
DECODE LOGIC
OUTPUT LATCHES &
BUFFERS
4
45
8
GAIN
DRRB DR,DRB
GORB
DATA,DATAB OR,ORB
MASTER/SLAVE TRACK & HOLD AMPLIFIER
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| TS8308J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Converter IC |
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