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參數資料
| 型號： | TS8388BCFB/Q |
| 廠商： | ATMEL CORP |
| 元件分類： | ADC |
| 英文描述： | 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數： | 43/47頁 |
| 文件大小： | 1230K |
| 代理商： | TS8388BCFB/Q |
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5
TS8388BF
2144A–BDC–04/02
Analog Inputs
Full Scale Input Voltage range (differential mode)
(0V common mode voltage)
V
IN
V
INB
4
–
-125
–
125
mV
Full Scale Input Voltage range (single-ended input
option) (See Application Notes)
V
IN
V
INB
4
–
-250
–
0
250
–
mV
Analog input capacitance
C
IN
4–
33.5
pF
Input bias current
IIN
4
–
10
20
A
Input Resistance
R
IN
40.5
1
–
M
Full Power input Bandwidth
FPBW
4
1.3
1.5
–
GHz
Small signal input Bandwidth (10% full scale)
SSBW
4
1.5
1.7
–
GHz
Clock Inputs
Logic compatibility for clock inputs
(See Application Notes)
––
ECL or specified clock input
power level in dBm
–
ECL Clock inputs voltages (V
CLK or VCLKB):
–
4
–
Logic “0” voltage
VIL
––
–
-1.5
V
Logic “1” voltage
V
IH
–-1.1
–
V
Logic “0” current
I
IL
––
5
50
A
Logic “1” current
IIH
––
5
50
A
Clock input power level into 50
termination
–
dBm into 50
–
Clock input power level
–
4
-2
4
10
dBm
Clock input capacitance
CCLK
4–
33.5
pF
Digital Outputs
Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format,
Tj (typical) = 70
°C.
Logic compatibility for digital outputs
(Depending on the value of V
PLUSD)
(See Application Notes)
–
ECL or LVDS
–
Differential output voltage swings
(assuming V
PLUSD = 0V):
–4
–
75
open transmission lines (ECL levels)
–
1.5
1.620
–
V
75
differentially terminated
–
0.70
0.825
–
V
50
differentially terminated
–
0.54
0.660
–
V
Output levels (assuming V
PLUSD = 0V)
75
open transmission lines:
–4
–
Logic “0” voltage
V
OL
––
-1.62
-1.54
V
Logic “1” voltage
V
OH
–
-0.88
-0.8
–
V
Table 3. Electrical Specifications (Continued)
Parameter
Symbol
Test
Level
Value
Unit
Note
Min
Typ
Max
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