
1
Features
8-bit Resolution
ADC Gain Adjust
1.5 GHz Full Power Input Bandwidth (-3 dB)
1 GSPS (min) Sampling Rate
SINAD = 44.3 dB (7.2 Effective Bits), SFDR = 58 dBc,
at F
S = 1 GSPS, FIN = 20 MHz
SINAD = 42.9 dB (7.0 Effective Bits), SFDR = 52 dBc,
at F
S = 1 GSPS, FIN = 500 MHz
SINAD = 40.3 dB (6.8 Effective Bits), SFDR = 50 dBc,
at FS = 1 GSPS, FIN = 1000 MHz (-3 dB FS)
2-tone IMD: -52 dBc (489 MHz, 490 MHz) at 1 GSPS
DNL = 0.3 lsb, INL = 0.7 lsb
Low Bit Error Rate (10-13) at 1 GSPS
Very Low Input Capacitance: 3 pF
500 mVpp Differential or Single-ended Analog Inputs
Differential or Single-ended 50
ECL Compatible Clock Inputs
ECL or LVDS/HSTL Output Compatibility
Data Ready Output with Asynchronous Reset
Gray or Binary Selectable Output Data; NRZ Output Mode
Power Consumption: 3.4W at Tj = 70
°C Typical
Radiation Tolerance Oriented Design (150 Krad (Si) measured)
Two Package Versions
ESA/SCC Detailed Specification Available on Request
Enhanced CQFP68 Packaged Device: TS8388BFS
Evaluation board: TSEV8388BF
Demultiplexer: TS81102G0: Companion Device Available
Applications
Digital Sampling Oscilloscopes
Satellite Receiver
Electronic Countermeasures/Electronic Warfare
Direct RF Down-conversion
Screening
Atmel Standard Screening Level
Mil-PRF-38535, QML Level Q for Package Version, DSCC 5962-0050401QYC
Temperature Range: up to -55
°C < Tc; Tj < +125°C
Description
The TS8388BF is a monolithic 8-bit analog-to-digital converter, designed for digitizing
wide bandwidth analog signals at very high sampling rates of up to 1 GSPS.
The TS8388BF uses an innovative architecture,
including an on-chip Sample and Hold (S/H),
and is fabricated with an advanced
high speed bipolar process.
The on-chip S/H has a 1.5 GHz full power
input bandwidth, providing excellent dynamic
performance in undersampling applications
(High IF digitizing).
ADC 8-bit
1 GSPS
TS8388BF
Rev. 2144A–BDC–04/02
F Suffix: CQFP 68
Ceramic Quad Flat Pack