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參數資料
| 型號： | TS8388BVFB/Q |
| 廠商： | ATMEL CORP |
| 元件分類： | ADC |
| 英文描述： | 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數： | 12/47頁 |
| 文件大小： | 1230K |
| 代理商： | TS8388BVFB/Q |
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2
TS8388BF
2144A–BDC–04/02
Functional
Description
Block Diagram
The following figure shows the simplified block diagram.
Figure 1. Simplified Block Diagram
Functional
Description
The TS8388BF is an 8-bit 1 GSPS ADC based on an advanced high-speed bipolar technology
featuring a cutoff frequency of 25 GHz.
The TS8388BF includes a front-end master/slave Track and Hold stage (S/H), followed by an
analog encoding stage and interpolation circuitry.
Successive banks of latches regenerate the analog residues into logical data before entering
an error correction circuitry and a resynchronization stage followed by 75
differential output
buffers.
The TS8388BF works in fully differential mode from analog inputs up to digital outputs.
The TS8388BF features a full-power input bandwidth of 1.5 GHz.
A control pin GORB is provided to select either Gray or Binary data output format.
A gain control pin is provided in order to adjust the ADC gain.
A Data Ready output asynchronous reset (DRRB) is available on TS8388BF.
The TS8388BF uses only vertical isolated NPN transistors together with oxide isolated polysil-
icon resistors, which allow enhanced radiation tolerance (no performance drift measured at
150 kRad total dose).
MASTER/SLAVE TRACK & HOLD AMPLIFIER
VIN, VINB
CLOCK
BUFFER
GAIN
GORB
DATA, DATAB OR, ORB
DRRB DR, DRB
CLK, CLKB
4
5
4
5
8
G=2
T/H
G=1
T/H
G=1
RESISTOR
CHAIN
ANALOG
ENCODING
BLOCK
INTERPOLATION
STAGES
REGENERATION
LATCHES
ERROR CORRECTION &
DECODE LOGIC
OUTPUT LATCHES &
BUFFERS
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相關代理商/技術參數 |
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|---|---|
| TS8388BVFS | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BVGL | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BVGL (+LID) | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
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