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參數(shù)資料
型號(hào)： TS8388BCFB/Q
廠商： E2V TECHNOLOGIES PLC
元件分類： ADC
英文描述： 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
封裝： CERAMIC, QFP-68
文件頁(yè)數(shù)： 45/47頁(yè)
文件大小： 1230K
代理商： TS8388BCFB/Q
7
TS8388BF
2144A–BDC–04/02
AC Performance
Single-ended or differential input and clock mode, 50% clock duty cycle (CLK, CLKB), Binary output data format,
Tj = 70
°C, unless otherwise specified.
Signal to Noise and Distortion ratio
SINAD
––
–
F
S = 1 GSPS, FIN = 20 MHz
4
42
44
–
dB
F
S = 1 GSPS, FIN = 500 MHz
4
41
43
–
dB
FS = 1 GSPS, FIN = 1000 MHz (-1 dBFs)
4
38
40
–
dB
F
S = 50 MSPS, FIN = 25 MHz
1, 2, 6
40
44
–
dB
Effective Number Of Bits
ENOB
––
–
FS = 1 GSPS, FIN = 20 MHz
4
7.0
7.2
–
Bits
F
S = 1 GSPS, FIN = 500 MHz
4
6.6
6.8
–
Bits
F
S = 1 GSPS, FIN = 1000 MHz (-1 dBFs)
4
6.2
6.4
–
Bits
FS = 50 MSPS, FIN = 25 MHz
1, 2, 6
7.0
7.2
–
Bits
Signal to Noise Ratio
SNR
––
–
F
S = 1 GSPS, FIN = 20 MHz
4
42
45
–
dB
FS = 1 GSPS, FIN = 500 MHz
4
41
44
–
dB
F
S = 1 GSPS, FIN = 1000 MHz (-1 dBFs)
4
41
44
–
dB
F
S = 50 MSPS, FIN = 25 MHz
1, 2, 6
44
45
–
dB
Total Harmonic Distortion
THD
––
–
F
S = 1 GSPS, FIN = 20 MHz
4
50
54
–
dB
F
S = 1 GSPS, FIN = 500 MHz
4
46
50
–
dB
FS = 1 GSPS, FIN = 1000 MHz (-1 dBFs)
4
42
46
–
dB
F
S = 50 MSPS, FIN = 25 MHz
1, 2, 6
46
45
–
dB
Spurious Free Dynamic Range
SFDR
––
–
FS = 1 GSPS, FIN = 20 MHz
4
52
57
–
dBc
F
S = 1 GSPS, FIN = 500 MHz
4
47
52
–
dBc
F
S = 1 GSPS, FIN = 1000 MHz (-1 dBFs)
4
42
47
–
dBc
FS = 1 GSPS, FIN = 1000 MHz (-3 dBFs)
4
45
50
–
dBc
F
S = 50 MSPS, FIN = 25 MHz
1, 2, 6
40
54
–
dBc
Two-tone Inter-modulation Distortion
IMD
4–
–
FIN1 = 489 MHz at FS = 1 GSPS,
F
IN2 = 490 MHz at FS = 1 GSPS
–-47
-52
–
dBc
Switching Performance and Charcteristics – See Figure 2 and Figure 3 on page 9
Maximum clock frequency
F
S
–
1
–
1.4
GSPS
Minimum clock frequency
F
S
4
10–50
MSPS
Minimum Clock pulse width (high)
TC1
4
0.280
0.500
50
ns
Table 3. Electrical Specifications (Continued)
Parameter
Symbol
Test
Level
Value
Unit
Note
Min
Typ
Max
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