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參數資料
| 型號： | TS8388BCFSB/Q |
| 廠商： | ATMEL CORP |
| 元件分類： | ADC |
| 英文描述： | 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數： | 17/47頁 |
| 文件大小： | 1230K |
| 代理商： | TS8388BCFSB/Q |
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TS8388BF
2144A–BDC–04/02
Consequently, minimum values for TOD and TDR are never more than 100 ps apart. The
same is true for the TOD and TDR maximum values.
In other terms :
–
If TOD is at 1150 ps, TDR will not be at 1620 ps (maximum time delay for TDR).
–
If TOD is at 1660 ps, TDR will not be at 1110 ps (minimum time delay for TDR).
However, external TOD-TDR values may be dictated by total digital datas skews
between every TODs (each digital data) and TDR: MCM Board, bonding wires and
output lines lengths differences, and output termination impedance mismatches.
The external (on board) skew effect has NOT been taken into account for the specification of
the minimum and maximum values for TOD-TDR.
Principle of Operation
The Analog input is sampled on the rising edge of external clock input (CLK, CLKB) after TA
(aperture delay) of typically 250 ps. The digitized data is available after 4 clock periods latency
(pipeline delay (TPD)), on clock rising edge, after 1360 ps typical propagation delay TOD.
The Data Ready differential output signal frequency (DR, DRB) is half the external clock fre-
quency, that is it switches at the same rate as the digital outputs.
The Data Ready output signal (DR, DRB) switches on external clock falling edge after a prop-
agation delay TDR of typically 1320 ps.
A Master Asynchronous Reset input command DRRB (ECL compatible single-ended input) is
available for initializing the differential Data Ready output signal (DR, DRB). This feature is
mandatory in certain applications using interleaved ADCs or using a single ADC with demulti-
plexed outputs. Actually, without Data Ready signal initialization, it is impossible to store the
output digital datas in a defined order.
Principle of Data
Ready Signal
Control by DRRB
Input Command
Data Ready Output
Signal Reset
The Data Ready signal is reset on falling edge of DRRB input command, on ECL logical low
level (-1.8V). DRRB may also be tied to V
EE = -5V for Data Ready output signal Master Reset.
So long DRRB remains at logical low level, (or tied to V
EE = -5V), the Data Ready output
remains at logical zero and is independant of the external free running encoding clock.
The Data Ready output signal (DR, DRB) is reset to logical zero after TRDR = 920 ps typical.
TRDR is measured between the -1.3V point of the falling edge of DRRB input command and
the zero crossing point of the differential Data Ready output signal (DR, DRB).
The Data Ready Reset command may be a pulse of 1 ns minimum time width.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TS8388BCG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A/D CONVERTER |
| TS8388BCGL | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BCGL (+LID) | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BMF | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BMFB/Q | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
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