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參數(shù)資料
| 型號(hào)： | TS8388BCGL |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA68 |
| 封裝： | 1.27 MM PITCH, CERAMIC, BGA-68 |
| 文件頁數(shù)： | 44/62頁 |
| 文件大小： | 1267K |
| 代理商： | TS8388BCGL |
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49
0860E–BDC–05/07
e2v semiconductors SAS 2007
TS8388B
10.5
Definitions
10.5.1
Definition of Terms
10.5.1.1
(BER) Bit Error Rate
Probability to exceed a specified error threshold for a sample. An error code is a code that differs by
more than ± 4 lsb from the correct code.
10.5.1.2
(FPBW) Full Power Input Bandwidth
Analog input frequency at which the fundamental component in the digitally reconstructed output has
fallen by 3 dB with respect to its low frequency value (determined by FFT analysis) for input at Full Scale.
10.5.1.3
(SINAD) Signal to Noise and Distortion Ratio
Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below Full Scale, to the RMS sum of all
other spectral components, including the harmonics except DC.
10.5.1.4
(SNR) Signal to Noise Ratio
Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below Full Scale, to the RMS sum of all
other spectral components excluding the five first harmonics.
10.5.1.5
(THD) Total Harmonic Distortion
Ratio expressed in dBc of the RMS sum of the first five harmonic components, to the RMS value of the
measured fundamental spectral component.
10.5.1.6
(SFDR) Spurious Free Dynamic Range
Ratio expressed in dB of the RMS signal amplitude, set at 1 dB below Full Scale, to the RMS value of the
next highest spectral component (peak spurious spectral component). SFDR is the key parameter for
selecting a converter to be used in a frequency domain application (Radar systems, digital receiver, net-
work analyzer, etc.). It may be reported in dBc (that is: degrades as signal levels is lowered), or in dBFS
(that is: always related back to converter full scale).
10.5.1.7
(ENOB) Effective Number of Bits
Where A is the actual input amplitude and V is the full scale range of the ADC under test.
10.5.1.8
(DNL) Differential Non Linearity
The Differential Non Linearity for an output code i is the difference between the measured step size of
code i and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL is the maximum value of all DNL
(i). DNL error specification of less than 1 lsb guarantees that there are no missing output codes and that
the transfer function is monotonic.
10.5.1.9
(INL) Integral Nonlinearity
The Integral Non Linearity for an output code i is the difference between the measured input voltage at
which the transition occurs and the ideal value of this transition.
INL (i) is expressed in LSBs, and is the maximum value of all |INL (i)|.
SINAD - 1.76 + 20 log (A/V/2)
6.02
ENOB =
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PDF描述 |
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| TS8388BMFS | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| TS8388BVGL | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA68 |
| TS8388BMFSB/T | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| TS8388BVFS | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
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| TS8388BCGL (+LID) | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
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