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參數資料
| 型號： | TS8388BMFB/Q |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數： | 12/44頁 |
| 文件大小： | 850K |
| 代理商： | TS8388BMFB/Q |
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TS8388BF
Preliminary Beta-Site
Specification
TABLE OF CONTENTS
1.
SIMPLIFIED BLOCK DIAGRAM.................................................................................................................................... 3
2.
FUNCTIONAL DESCRIPTION ........................................................................................................................................ 3
3.
SPECIFICATIONS............................................................................................................................................................. 4
3.1.
ABSOLUTE MAXIMUM RATINGS (SEE NOTES BELOW) ...............................................................................................................................4
3.2.
RECOMMENDED CONDITIONS OF USE ..........................................................................................................................................................4
3.3.
ELECTRICAL OPERATING CHARACTERISTICS .............................................................................................................................................5
3.4.
TIMING DIAGRAMS .............................................................................................................................................................................................9
3.5.
EXPLANATION OF TEST LEVELS ...................................................................................................................................................................10
3.6.
WAFER SCREENING ........................................................................................................................................................................................10
3.7.
FUNCTIONS DESCRIPTION.............................................................................................................................................................................11
3.8.
DIGITAL OUTPUT CODING ..............................................................................................................................................................................11
4.
PACKAGE DESCRIPTION............................................................................................................................................. 12
4.1.
TS8388BF PIN DESCRIPTION .........................................................................................................................................................................12
4.2.
TS8388BF PINOUT ............................................................................................................................................................................................13
4.3.
OUTLINE DIMENSIONS – 68 PINS CQFP .......................................................................................................................................................14
4.4.
THERMAL CHARACTERISTICS .......................................................................................................................................................................15
5.
TYPICAL CHARACTERIZATION RESULTS.............................................................................................................. 16
5.1.
STATIC LINEARITY – FS = 50 MSPS / FIN = 10 MHZ.....................................................................................................................................16
5.2.
EFFECTIVE NUMBER OF BITS VERSUS POWER SUPPLIES VARIATION.................................................................................................17
5.3.
TYPICAL FFT RESULTS ...................................................................................................................................................................................18
5.4.
SPURIOUS FREE DYNAMIC RANGE VERSUS INPUT AMPLITUDE............................................................................................................19
5.5.
DYNAMIC PERFORMANCE VERSUS ANALOG INPUT FREQUENCY.........................................................................................................20
5.6.
EFFECTIVE NUMBER OF BITS (ENOB) VERSUS SAMPLING FREQUENCY .............................................................................................21
5.7.
SFDR VERSUS SAMPLING FREQUENCY......................................................................................................................................................21
5.8.
TS8388BF ADC PERFORMANCES VERSUS JUNCTION TEMPERATURE .................................................................................................22
5.9.
TYPICAL FULL POWER INPUT BANDWIDTH ................................................................................................................................................23
5.10.
ADC STEP RESPONSE ................................................................................................................................................................................24
6.
DEFINITION OF TERMS ............................................................................................................................................... 25
7.
APPLYING THE TS8388BF............................................................................................................................................ 27
7.1.
TIMING INFORMATIONS ..................................................................................................................................................................................27
7.2.
PRINCIPLE OF DATA READY SIGNAL CONTROL BY DRRB INPUT COMMAND ......................................................................................28
7.3.
ANALOG INPUTS (VIN) (VINB) .........................................................................................................................................................................28
7.4.
CLOCK INPUTS (CLK) (CLKB)..........................................................................................................................................................................29
7.5.
CLOCK SIGNAL DUTY CYCLE ADJUST .........................................................................................................................................................31
7.6.
NOISE IMMUNITY INFORMATIONS ................................................................................................................................................................31
7.7.
DIGITAL OUTPUTS............................................................................................................................................................................................32
7.8.
OUT OF RANGE BIT ..........................................................................................................................................................................................35
7.9.
GRAY OR BINARY OUTPUT DATA FORMAT SELECT..................................................................................................................................35
7.10.
DIODE PIN 49 ................................................................................................................................................................................................35
7.11.
ADC GAIN CONTROL PIN 60.......................................................................................................................................................................36
8.
EQUIVALENT INPUT / OUTPUT SCHEMATICS ....................................................................................................... 37
8.1.
EQUIVALENT ANALOG INPUT CIRCUIT AND ESD PROTECTIONS ...........................................................................................................37
8.2.
EQUIVALENT ANALOG CLOCK INPUT CIRCUIT AND ESD PROTECTIONS..............................................................................................37
8.3.
EQUIVALENT DATA OUTPUT BUFFER CIRCUIT AND ESD PROTECTIONS .............................................................................................38
8.4.
ADC GAIN ADJUST EQUIVALENT INPUT CIRCUITS AND ESD PROTECTIONS .......................................................................................38
8.5.
GORB EQUIVALENT INPUT SCHEMATIC AND ESD PROTECTIONS .........................................................................................................39
8.6.
DRRB EQUIVALENT INPUT SCHEMATIC AND ESD PROTECTIONS .........................................................................................................40
9.
TSEV8388BF : DEVICE EVALUATION BOARD ......................................................................................................... 41
10.
ORDERING INFORMATION..................................................................................................................................... 42
10.1.
PACKAGE DEVICE........................................................................................................................................................................................42
10.2.
EVALUATION BOARD...................................................................................................................................................................................42
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| TS8388BMF | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TS8388BMFS | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BMFS9NB1 | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BMFS9NB2 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:ADC 8-bit 1 GSPS |
| TS8388BMFS9NB3 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:ADC 8-bit 1 GSPS |
| TS8388BMFS9NC2 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:ADC 8-bit 1 GSPS |
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