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參數(shù)資料
| 型號： | TS8388BVFS9NC3ZB9 |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數(shù)： | 26/43頁 |
| 文件大小： | 825K |
| 代理商： | TS8388BVFS9NC3ZB9 |
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TS8388BFS
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Preliminary Beta Site
7.7.
DIGITAL OUTPUTS
The TS8388BFS differential output buffers are internally 75 ohms loaded. The 75 ohms resistors are connected to the digital ground pins
through a -0.8v level shift diode (see Figures 3,4,5 on next page).
The TS8388BFS output buffers are designed for driving 75 ohms (default) or 50 ohms properly terminated impedance lines or coaxial cables.
An 11 mA bias current flowing alternately into one of the 75 ohms resistors when switching ensures a 0.825 V voltage drop across the resistor
(unterminated outputs).
The VPLUSD positive supply voltage allows the adjustment of the output common mode level from -1.2V (VPLUSD=0V for ECL output
compatibility) to +1.2V (VPLUSD=2.4V for LVDS output compatibility).
Therefore,the single ended output voltages vary approximately between -0.8V and -1.625V, ( outputs unterminated ), around -1.2V common
mode voltage.
Three possible line driving and back-termination scenarios are proposed (assuming VPLUSD=0V) :
1 ) 75 Ohms impedance transmission lines, 75 ohms differentialy terminated (Fig. 3) :
Each output voltage varies between -1V and -1.42V (respectively +1.4V and +1V), leading to +/- 0.41V =0.825 V in differential, around -1.21 V
(respectively +1.21V) common mode for VPLUSD=0V (respectively 2.4V).
2 ) 50 ohms impedance transmission lines, 50 ohms differentialy termination (Fig. 4) :
Each output voltage varies between -1.02V and -1.35V (respectively +1.38V and +1.05V), leading to +/- 0.33V=660 mV in differential, around -
1.18V (respectively +1.21V) common mode for VPLUSD=0V (respevtively 2.4V).
3 ) 75 ohms impedance open transmission lines (Fig. 5) :
Each output voltage varies between -1.6 V and -0.8 V (respectively +0.8V and +1.6V), which are true ECL levels, leading to +/- 0.8V=1.6V in
differential, around -1.2V (respectively +1.2V) common mode for VPLUSD=0V (respectively 2.4V).
Therefore, it is possible to drive directly high input impedance storing registers, without terminating the 75 ohms transmission lines.
In time domain, that means that the incident wave will reflect at the 75 ohms transmission line output and travel back to the generator ( i.e. the
75 ohms data output buffer ). As the buffer output impedance is 75 ohms, no back reflection will occur.
Note : This is no longer true if a 50 ohms transmission line is used, as the latter is not matching the buffer 75 ohms output impedance.
Each differential output termination length must be kept identical .
It is recommended to decouple the midpoint of the differential termination with a 10 nF capacitor to avoid common mode perturbation in case of
slight mismatch in the differential output line lengths.
Too large mismatches ( keep < a few mm ) in the differential line lengths will lead to switching currents flowing into the decoupling capacitor
leading to switching ground noise.
The differential output voltage levels ( 75 or 50 ohms termination ) are not ECL standard voltage levels, however it is possible to drive standard
logic ECL circuitry like the ECLinPS logic line from MOTOROLA.
At sampling rates exceeding 1GSPS, it may be difficult to trigger the HP16500 or any other Acquisition System with digital outputs.
It becomes necessary to regenerate digital data and Data Ready by means of external amplifiers, in order to be able to test the TS8388BFS at
its optimum performance conditions.
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