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參數資料
型號: TS8388BVFS
廠商: E2V TECHNOLOGIES PLC
元件分類: ADC
英文描述: 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
封裝: CERAMIC, QFP-68
文件頁數: 45/62頁
文件大小: 1267K
代理商: TS8388BVFS
5
0860E–BDC–05/07
e2v semiconductors SAS 2007
TS8388B
Nominal power dissipation
PD
1, 2
6
3.4
3.6
4.1
4.3
W
Power supply rejection ratio
PSRR
4
0.5
2
mV/V
Resolution
8
bits
Analog Inputs
Full Scale Input Voltage range (differential mode)
(0V common mode voltage)
VIN
V
INB
4
125
125
mV
Full Scale Input Voltage range (single-ended input
option) (See Application Notes)
VIN
V
INB
4
250
0
250
mV
Analog input capacitance
CIN
4–
3
3.5
pF
Input bias current
IIN
4
10
20
A
Input Resistance
R
IN
40.5
1
M
Full Power input Bandwidth (–3dB)
CBGA68 package
CQFP68 package
FPBW
4
1.8
1.5
GHz
Small signal input Bandwidth (10% full scale)
SSBW
4
1.5
1.7
GHz
Clock Inputs
Logic compatibility for clock inputs
(See Application Notes)
––
ECL or specified clock input
power level in dBm
ECL Clock inputs voltages (V
CLK or VCLKB):
4
–––
Logic “0” voltage
V
IL
––
1.5
V
Logic “1” voltage
VIH
1.1
V
Logic “0” current
I
IL
––
5
50
A
Logic “1” current
I
IH
––
5
50
A
Clock input power level into 50
termination
dBm into 50
Clock input power level
4
2410
dBm
Clock input capacitance
C
CLK
4–
3
3.5
pF
Digital Outputs
Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format,
T
J (typical) = 70°C.
Logic compatibility for digital outputs
(Depending on the value of V
PLUSD)
(See Application Notes)
––
ECL or LVDS
Differential output voltage swings
(assuming VPLUSD = 0V):
4
–––
75
open transmission lines (ECL levels)
1.5
1.620
V
75
differentially terminated
0.70
0.825
V
Table 5-3.
Electrical Specifications (Continued)
Parameter
Symbol
Test
Level
Value
Unit
Note
Min
Typ
Max
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