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參數(shù)資料
型號(hào)： TS8388BVGL
廠商： E2V TECHNOLOGIES PLC
元件分類： ADC
英文描述： 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA68
封裝： 1.27 MM PITCH, CERAMIC, BGA-68
文件頁(yè)數(shù)： 21/62頁(yè)
文件大小： 1267K
代理商： TS8388BVGL
28
0860E–BDC–05/07
TS8388B
e2v semiconductors SAS 2007
8.
TS8388B Main Features
8.1
Timing Information
8.1.1
Timing Value for TS8388B
Timing values as defined in Table 5-3 on page 4 are advanced data, issued from electric simulations and
first characterizations results fitted with measurements.
Timing values are given at package inputs/outputs, taking into account package internal controlled
impedance traces propagation delays, gullwing pin model, and specified termination loads.
Propagation delays in 50/75
impedance traces are not taken into account for TOD and TDR.
Apply proper derating values corresponding to termination topology.
The min/max timing values are valid over the full temperature range in the following conditions:
Specified Termination Load (Differential output Data and Data Ready):
50
resistor in parallel with 1 standard ECLinPS register from Freescale (that is: 10E452)
Typical ECLinPS inputs shows a typical input capacitance of 1.5 pF (including package and ESD
protections).
If addressing an output DMUX, take care if some Digital outputs do not have the same termination
load and apply corresponding derating value given below.
Output Termination Load derating values for TOD and TDR:
~ 35 ps/pF or 50 ps per additional ECLinPS load.
Propagation time delay derating values have also to be applied for TOD and TDR:
~ 6 ps/mm (155 ps/inch) for TSEV8388B Evaluation Board.
Apply proper time delay derating value if a different dielectric layer is used.
8.1.2
Propagation Time Considerations
TOD and TDR Timing values are given from pin to pin and do not include the additional propagation
times between device pins and input/output termination loads. For the TSEV8388B Evaluation Board,
the propagation time delay is 6 ps/mm (155 ps/inch) corresponding to 3.4 (at 10 GHz) dielectric constant
of the RO4003 used for the board.
If a different dielectric layer is used (for instance Teflon), please use appropriate propagation time
values.
TD does not depend on propagation times because it is a differential data (TD is the time difference
between data ready output delay and digital data output delay).
TD is also the most straightforward data to measure, again because it is differential: TD can be mea-
sured directly onto termination loads, with matched oscilloscopes probes.
8.1.3
TOD-TDR Variation Over Temperature
Values for TOD and TDR track each other over temperature (1% variation for TOD-TDR per 100
°C tem-
perature variation).
Therefore TOD-TDR variation over temperature is negligible. Moreover, the internal (on-chip) and pack-
age skews between each Data TODs and TDR effect can be considered as negligible.
Consequently, minimum values for TOD and TDR are never more than 100 ps apart. The same is true
for the TOD and TDR maximum values.
相關(guān)PDF資料
PDF描述
TS8388BMFSB/T 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
TS8388BVFS 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
TS8388BMF 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
TS8388BCFS 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
TS8388BCF 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
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