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參數(shù)資料
型號(hào): TS86101G2BMGS
廠商: ATMEL CORP
元件分類: DAC
英文描述: SERIAL INPUT LOADING, 10-BIT DAC, PBGA255
封裝: CI-CGA-255
文件頁數(shù): 36/57頁
文件大小: 1119K
代理商: TS86101G2BMGS
41
5343C–BDC–03/06
TS86101G2B
12.3
CW_IN Master Clock Implementation
In order to allow for any ECL/PECL/LVDS differential input levels, the CW_IN master input clock
must be AC-coupled through 10 nF capacitors (for information only) as shown in Figure 12-8.
Figure 12-8. CW_IN Master Input Clock Implementation in AC-coupled Differential Mode
Figure 12-9. CW_IN Master Input Clock Implementation in AC-coupled Singled-ended Mode
12.4
DSP Output Clock Implementation
In order to make the DSP output clock compatible with standard differential levels such as LVDS
and PECL, the signals must be AC-coupled with 10 pF capacitors and used with pull-down resis-
tors to ensure appropriate biasing, as shown in the following three figures.
Three configurations are depicted:
The load has a high impedance input buffer
The load has a 100
differential buffer
The DSP_CLK is sent to the load via a driver
CW_IN_T
CW_IN_F
VEEA
50
Driving
Source
10 nF
CW Input
Buffer
AGND
50
MUXDAC
50
lines
500
450
-10 dBm (200 mVpp) to
+2 dBm (800 mVpp) max
-10 dBm (200 mVpp) to
+2 dBm (800 mVpp) max
CW_IN_T
CW_IN_F
VEEA
50
Driving
Source
10 nF
CW Input
Buffer
AGND
50
AGND
50
MUXDAC
50
Lines
500
450
-4 dBm (400 mVpp) to
+8 dBm (1.6 Vpp) max
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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