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參數資料
| 型號： | TSA1401IFT |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | ADC |
| 英文描述： | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | 7 X 7 MM, TQFP-48 |
| 文件頁數： | 7/19頁 |
| 文件大小： | 641K |
| 代理商： | TSA1401IFT |
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APPLICATION INFORMATION
TSA1401
15/19
5.3 - Power consumption optimization
The internal architecture of the TSA1401 enables
the
optimization
of
the
power
consumption
according to the sampling frequency of the
application. For this purpose, a resistor (value
Rpol) is placed between IPOL and the analog
Ground pins. At 20MHz sampling frequency, the
Rpol for optimized consumption is equal to 41k
.
Optimized power consumption of the circuit
versus the sampling frequency are shown in two
configurations (
l REFMODE=0 internal references
l REFMODE=1 external references
Fig. 18: Analog Current consumption vs. Fs
According value of Rpol polarization
resistances: internal references
5.4 - Digital outputs
Data Format Select (DFSB)
When set to low level (VIL), the digital input DFSB
provides a two’s complement digital output MSB.
This can be of interest when performing some
further signal processing.
When set to high level (VIH), DFSB provides a
standard binary output coding.
Output Enable (OEB)
When set to low level (VIL), all digital outputs
remain active and are in low impedance state.
When set to high level (VIH), all digital outputs
buffers are in high impedance state. It results in
lower consumption while the converter goes on
sampling.
When OEB is set to low level again, the data is
then valid on the output with a very short Ton
delay(1ns).
The timing diagram page 4 summarizes this
operating cycle.
Out of Range (OR)
This function is implemented on the output stage
in order to set up an "Out of Range" flag whenever
the digital data is over the full scale range.
Typically, there is a detection of all the data being
at ’0’ or all the data being at ’1’. This ends up with
an output signal OR which is in low level state
(VOL) when the data stay within the range, or in
high level state (VOH) when the data are out of
the range.
Data Ready (DR)
The Data Ready output is an image of the clock
being synchronized on the output data (D0 to
D13). This is a very helpful signal that simplifies
the
synchronization
of
the
measurement
equipment or the controlling DSP.
As digital output, DR goes in high impedance
state when OEB is asserted to High level as
described in the timing diagram page 4.
5.5 - Layout precautions
To use the TSA1401 circuit in the best manner at
high frequencies, some precautions have to be
taken for power supplies:
- The separation of the analog signal from the
digital part and from the buffers power supply is
essential to prevent noise from coupling onto the
input signal.
- Power supply bypass capacitors must be placed
as close as possible to the IC pins in order to
improve high frequency bypassing and reduce
harmonic distortion.
- Proper termination of all inputs and outputs is
needed; with output termination resistors, the
amplifier load will be only resistive and the stability
of the amplifier will be improved. All leads must be
wide and as short as possible especially for the
analog input in order to decrease parasitic
capacitance and inductance.
20
25
30
35
40
45
510
15
20
Fs (Mhz)
Ipol
(
m
A)
0
20
40
60
80
100
120
140
Rpol
(
ohm
)
Ipol_intre f
Ipol_e xtre f
Rpol
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