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參數(shù)資料
型號(hào)： TSB12LV01BPZ
英文描述： FPGA (Field-Programmable Gate Array)
中文描述： 總線控制器
文件頁(yè)數(shù)： 100/106頁(yè)
文件大小： 605K
代理商： TSB12LV01BPZ
8
–
7
been transferred. The Phy indicates the end of packet data by asserting idle on the CTL terminals. All
received packets are transferred to the TSB12LV32. Note that the speed code is part of the Phy-LLC
protocol and is not included in the calculation of CRC or any other data protection mechanisms.
It is possible for the Phy to receive a null packet, which consists of the data-prefix state on the serial bus
followed by the data-end state, without any packet data. A null packet is transmitted whenever the packet
speed exceeds the capability of the receiving Phy, or whenever the TSB12LV32 immediately releases the
bus without transmitting any data. In this case, the Phy will assert receive on the CTL terminals with the
data-on indication (all 1s) on the D terminals, followed by idle on the CTL terminals, without any speed code
or data being transferred. In all cases, the TSB41LV03A sends at least one data-on indication before
sending the speed code or terminating the receive operation.
The TSB41LV03A also transfers its own self-ID packet, transmitted during the self-ID phase of bus
initialization, to the TSB12LV32. This packet it transferred to the TSB12LV32 just as any other received
self-ID packet.
00
00
10
00
01
XX
dn
d0
SPD
(a)
(e)
(d)
(b)
(c)
FF (
“
data
–
on
”
)
D0
–
D7
CTL0, CTL1
SYSCLK
Figure 8
–
4. Normal Packet Reception Timing
The sequence of events for a normal packet reception is as follows:
Receive operation initiated. The Phy indicates a receive operation by asserting receive on the
CTL lines. Normally, the interface is idle when receive is asserted. However, the receive operation
may interrupt a status transfer operation that is in progress so that the CTL lines may change from
status to receive without an intervening idle.
Data-on indication. The Phy asserts the data-on indication code on the D lines for one or more
cycles preceding the speed-code.
Speed-code. The Phy indicates the speed of the received packet by asserting a speed-code on
the D lines for one cycle immediately preceding packet data. The link decodes the speed-code
on the first receive cycle for which the D lines are not the data-on code. If the speed-code is
invalid, or indicates a speed higher than that which the link is capable of handling, the link should
ignore the subsequent data.
Receive data. Following the data-on indication (if any) and the speed-code, the Phy asserts
packet data on the D lines with receive on the CTL lines for the remainder of the receive operation.
Receive operation terminated. The Phy terminates the receive operation by asserting idle on the
CTL lines. The Phy asserts at least one cycle of idle following a receive operation.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB12LV01BPZT 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB12LV01BPZTG4 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB12LV01PZ 制造商:Rochester Electronics LLC 功能描述:- Bulk
TSB12LV21 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394 LINK LAYER CONTROLLER
TSB12LV21A 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 BUS TO PCI BUS INTERFACE
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