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參數資料
| 型號： | TSB43AA22PDT |
| 英文描述： | IC ARRIA GX FPGA 50K 484FBGA |
| 中文描述： | 控制器雜項-數據表參考 |
| 文件頁數： | 8/159頁 |
| 文件大?。?/td> | 1085K |
| 代理商： | TSB43AA22PDT |
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TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Page 8
2.1.1.
Physical Interface
The Physical (PHY) interface provides Phy-level service to the LINK layer service. In normal usage, this interface is
connected to internal PHY, but this interface module also allows connecting external PHY. This is useful when multiple
port PHY or Isolation is required.
2.1.2.
LINK_Core (1394.a)
The LINK_Core provide LINK layer service such as transmit and receive correctly formatted IEEE1394-1995 and
IEEE1394.a Asynchronous packets. Also generate and inspect the 32-bits cyclic redundancy check (CRC).
This LINK Core doesn’t have capable Isochronous Service.
2.1.3.
ConfigROM
The ConfigROM module support Auto Response service for Config ROM read request. And also record transaction
history. This module has 528byte of random access memory. ConfigROM provide Configuration ROM that required for
IEEE-1212 standard and Host controller can load its data during node initialization. Before all ConfigROM data is
loaded, LINK_Core return Ack_Tardy to all read requests for this address. Once initialized, ConfigROM is accessible by
peer Node read request.
Log module provides transaction history and has loop FIFO architecture.
Hostcontroller can read most recent transaction packet history that transmitted and received by this node.
(Note) Log Mode is disabled when ConfigRom or Status accesses.
Hostcontroller can set each memory size for above two modules. Refer to CFR 0x8C, 0xF8 and 0xFC for more
information.
2.1.4.
AutoResp
The AutoResp module provide auto packet response service for in-coming request packet.
This AutoResp work for ConfigROM read request, Agent State read request, and error response packet for Un-expected
packet. Some sort of auto error response packet could be disable by control bit for various protocols.
2.1.5.
MICRO I/F
The MICRO I/F module provides Hostcontroller interface. This module could be accessed by 8/16-bit access both of data
address multiplex, 8 bit address data parallel access, and also 16 bit data/8 bit address parallel access when using BDOx
line as address line. This interface has Indian programmable access, and allows most MicroController can access CFR
easily. Refer to section 3 for more information.
2.1.6.
CFR
The CFR(Configuration Resistor) provide most of control bits and also hostcontroller monitor for this node.
Refer to section 3 for more information.
2.1.7.
FOX
The FOX module provide Faster ORB exchanger (FOX) function and support Management ORB and also Command
block ORB transaction. In SBP-2 protocol, target has to read ORB packet from initiators.
This FOX module automatically read both of Management ORB and Command block ORB from initiator when Initiator
requested. Once Management Agent address (CFR 0x48) and other information is set, Hostcontroller does not
have to access each packet until getting ORB packet. Linked Command block ORB is automatically fetched each by each
and hardware can emulate up to 4 Agents.
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| TSB43AA82A | IC ARRIA GX FPGA 50K 780FBGA |
| TSB43AB21A | IC ARRIA GX FPGA 60K 484FBGA |
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| TSB43AA82I | 1394 INTEGRATED PHY AND LINK LAYER CONTROLLER |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TSB43AA22PDTG4 | 制造商:Texas Instruments 功能描述: |
| TSB43AA82 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394 INTEGRATED PHY AND LINK LAYER CONTROLLER |
| TSB43AA82A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2 Port High Performance Integrated Phy and Link Layer Chip for PC Peripherals |
| TSB43AA82AI | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394 Integrated PHY and Link-Layer Controller for SBP-2 Products and DPP Products |
| TSB43AA82AIPGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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