- 您現在的位置：買賣IC網 > PDF目錄365968 > TSB43AA22PDT IC ARRIA GX FPGA 50K 484FBGA PDF資料下載
參數資料
| 型號： | TSB43AA22PDT |
| 英文描述： | IC ARRIA GX FPGA 50K 484FBGA |
| 中文描述： | 控制器雜項-數據表參考 |
| 文件頁數： | 9/159頁 |
| 文件大小： | 1085K |
| 代理商： | TSB43AA22PDT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Page 9
This module have 2 FIFO modules for Management ORB and Command block ORB for both of transmit and receive
packet. Refer to CFR from 0x44 to 0x6C for more detail.
2.1.8.
Packet Distributor
The Packet Distributor module provides packet routing service for each FIFO module.
When SBP-2 mode, all of request packet and response packet have property and rutting to correct FIFO, and also sent to
corresponding initiators. W hen DPP mode, Packet Distributor filtering request packet by its addressing and save it into
correct receive FIFO. Refer to CFR definition for more detail.
2.1.9.
TRMgr
The TRMgr(Transaction Manager) module provide transaction control service which control packet transmit Priority
between control packet and Data packet. Management is simple first in first type control, so, any packet Transmit request
for cable is sent by its order. This module also control split transaction management and busy retry control. If
acknowledge packet for the sent packet is any busy code, module retry to send packet until the packet succeed to transmit
or busy time out. And also, if acknowledge packet for the sent packet is ack_pending, then module start split transaction
timer and waits response packet. If node did not receive Response packet until split transaction time out limit, then the
module set error code and set interrupt.
See CFR specification for more detail.
2.1.10.
Packetizer
The Packetizer module provide packetization for transmit packet. The data stream from BDIF and Bdffifi is split into
small packet that meet SBP-2 requirement. Read request or write request header is attached for each packet and each
header has correctly incremented destination address. These transaction also do busy retry and split transaction timer
control if required. Refer to section for more detail.
The packetizer also provide, AutoPage Table Fetch service, Internal Auto Fetch module send Read Request to page
present address each by each, and DMA automatically send Data to requested address that set by Page Table Element. At
the end of Packetizer, if entire DMA function is completed successfully, then Status Block Packet is automatically sent by
DMA.
2.1.11.
Bdffifo
The Bdffifo module provide data packet FIFO for SBP-2 read response packet and also write request packet. FIFO size is
4736 byte max including received header space, and FIFO size for each Tx and Rx is programmable that set by
Hostcontroller via CFR. Refer to CFR definition for more detail.
2.1.12.
BDif
The BDif module provides data interface between external host DMA and internal FIFO (Bdfifo).
Data is also could be read by Micro I/F in some condition if required. This interface has several mode such as 8/16 bit
width also asynch/synchronous mode. Refer to Bulky interface section for more detail.
相關PDF資料 |
PDF描述 |
|---|---|
| TSB43AA82A | IC ARRIA GX FPGA 50K 780FBGA |
| TSB43AB21A | IC ARRIA GX FPGA 60K 484FBGA |
| TSB43AB21A-EP | IC ARRIA GX FPGA 60K 1152FBGA |
| TSB43AA82I | 1394 INTEGRATED PHY AND LINK LAYER CONTROLLER |
| TSB43CA43AGGW | TI iceLynx-Micro⑩ IEEE 1394a-2000 Consumer Electronics Solution |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TSB43AA22PDTG4 | 制造商:Texas Instruments 功能描述: |
| TSB43AA82 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394 INTEGRATED PHY AND LINK LAYER CONTROLLER |
| TSB43AA82A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2 Port High Performance Integrated Phy and Link Layer Chip for PC Peripherals |
| TSB43AA82AI | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394 Integrated PHY and Link-Layer Controller for SBP-2 Products and DPP Products |
| TSB43AA82AIPGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
發布緊急采購，3分鐘左右您將得到回復。