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參數資料
| 型號： | TSC2046IZQCT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA48 |
| 封裝： | 4 X 4 MM, ROHS COMPLIANT, PLASTIC, VFBGA-48 |
| 文件頁數： | 29/33頁 |
| 文件大小： | 774K |
| 代理商： | TSC2046IZQCT |
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TSC2046
SBAS265G OCTOBER 2002 REVISED JANUARY 2008
www.ti.com
5
PIN CONFIGURATION
Top View
1
2
3
4
5
6
7
8
+V
CC
X+
Y+
X
Y
GND
V
BAT
AUX
DCLK
CS
DIN
BUSY
DOUT
PENIRQ
IOVDD
V
REF
16
15
14
13
12
11
10
9
TSC2046
Top View
QFN
TSSOP
Top View
VFBGA
NC
A
B
C
D
E
F
G
2
1
3
4
5
6
7
DCLK
+V
CC
+V
CC
X+
Y+
PENIRQ
IOVDD
V
REF
AUX
CS
DIN
BUSY DOUT
X
Y
GND
V
BAT
NC
BUSY
DIN
CS
DCLK
AUX
V
BAT
GND
Y
1
2
3
4
12
11
10
9
TSC2046
DO
U
T
PE
N
IR
Q
IO
V
D
V
RE
F
16
15
14
13
+V
CC
X+
Y+
X
5
6
7
8
(1) The thermal pad is internally connected to the substrate. This pad can be connected to the analog ground or left floating. Keep the thermal
pad separate from the digital ground, if possible.
(Thermal Pad)(1)
PIN DESCRIPTION
TSSOP PIN #
VFBGA PIN #
QFN PIN #
NAME
DESCRIPTION
1
B1 and C1
5
+VCC
Power Supply
2
D1
6
X+
X+ Position Input
3
E1
7
Y+
Y+ Position Input
4
G2
8
X
X Position Input
5
G3
9
Y
Y Position Input
6
G4 and G5
10
GND
Ground
7
G6
11
VBAT
Battery Monitor Input
8
E7
12
AUX
Auxiliary Input to ADC
9
D7
13
VREF
Voltage Reference Input/Output
10
C7
14
IOVDD
Digital I/O Power Supply
11
B7
15
PENIRQ
Pen Interrupt
12
A6
16
DOUT
Serial Data Output. Data are shifted on the falling edge of DCLK. This output is high
impedance when CS is high.
13
A5
1
BUSY
Busy Output. This output is high impedance when CS is high.
14
A4
2
DIN
Serial Data Input. If CS is low, data are latched on the rising edge of DCLK.
15
A3
3
CS
Chip Select Input. Controls conversion timing and enables the serial input/output register.
CS high = power-down mode (ADC only).
16
A2
4
DCLK
External Clock Input. This clock runs the SAR conversion process and synchronizes serial
data I/O.
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