
TSC2111
SLAS495A JUNE 2006 REVISED OCTOBER 2007
www.ti.com
78
BIT
FUNCTION
READ/
WRITE
RESET
VALUE
NAME
D5D3
CDEBSN
000
R
Debounce Time for Transition from Silence Mode to Normal Mode. This is Valid for
Cellphone AGC.
000 => 0 ms
001 => 0.5 ms
010 => 1.0 ms
011 => 2.0 ms
100 => 4.0 ms
101 => 8.0 ms
110 => 16.0 ms
111 => 32.0 ms
D2D0
000
R
Reserved (Write only 000)
TSC2111 Buffer Data Registers (Page 3)
The buffer data registers of the TSC2111 hold data results from the SAR ADC conversions in buffer mode. Upon
reset, bit D15 is set to 0, bit D14 is set to 1 and the remaining bits are don’tcare. These registers are read only.
If buffer mode is enabled, then the results of all ADC conversions are placed in the buffer data register. The
data format of the result word (R) of these registers is right-justified which is as follows:
D15
MSB
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LSB
FUF
EMF
X
ID
R11
MSB
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
LSB
BIT
NAME
RESET
VALUE
READ/
WRITE
FUNCTION
D15
FUF
0
R
Buffer Full Flag
This flag indicates that all the 64 locations of the buffer are having unread data.
D14
EMF
1
R
Buffer Empty Flag
This flag indicates that there is no unread data available in FIFO. This is generated while reading the
last converted data.
D13
X
R
Reserved
D12
ID
X
R
Data Identification
0 => X or Z1 coordinate or BAT or AUX2 data in R11R0
1 => Y or Z2 coordinate or AUX1 or TEMP data in R11R0
Order for Writing Data in Buffer When Multiple Inputs are Selected
For XY Conversion:
Y, X
For XYZ1Z2 Conversion:
Y, X, Z1, Z2
For Z1Z2 Conversion:
Z1, Z2
For Auto Scan Conversion: AUX1 (if selected), AUX2 (if selected), TEMP (if selected)
For Port Scan Conversion: BAT, AUX1, AUX2
D11D0
R11R0
X’s
R
Converted Data
LAYOUT
The following layout suggestions should provide optimum performance from the TSC2111. However, many
portable applications have conflicting requirements concerning power, cost, size, and weight. In general, most
portable devices have fairly clean power and grounds because most of the internal components are very low
power. This situation would mean less bypassing for the converter’s power and less concern regarding
grounding. Still, each situation is unique and the following suggestions should be reviewed carefully.
For optimum performance, care should be taken with the physical layout of the TSC2111 circuitry. The basic
SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground
connections, and digital inputs that occur just prior to latching the output of the analog comparator. Therefore,
during any single conversion for an n-bit SAR converter, there are n windows in which large external transient
voltages can easily affect the conversion result. Such glitches might originate from switching power supplies,
nearby digital logic, and high power devices. The degree of error in the digital output depends on the reference
voltage, layout, and the exact timing of the external event. The error can change if the external event changes
in time with respect to the timing of the critical n windows.