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參數(shù)資料
| 型號： | TSC2300IPAGR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | GREEN, PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 21/81頁 |
| 文件大?。?/td> | 1039K |
| 代理商： | TSC2300IPAGR |
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TSC2300
SLAS372 — NOVEMBER 2002
A/D Conversion Averaging Control (continued)
AV1
AV0
FUNCTION
0
1
4 data averages
1
0
8 data averages
1
16 data averages
Bits[5:4] — CL1, CL0
Conversion Clock Control. These two bits specify the internal clock rate which the A/D converter uses when performing
a conversion. See Table 11. These bits are the same whether reading or writing.
Table 11. A/D Converter Conversion Clock Control
CL1
CL0
FUNCTION
0
8-MHz internal clock rate - 8-bit resolution only (default)
0
1
4-MHz internal clock rate - 8- or 10-bit resolution only
1
0
2-MHz internal clock rate
1
1-MHz internal clock rate
Bits [3:1] — PV2 - PV0
Panel Voltage Stabilization Time control. These bits allow the user to specify a delay time from when a driver is turned
on to the time sampling begins and a conversion is started. In self-controlled mode, when a pen touch is detected, the
part first turns on a driver, waits a programmed delay time set by PV2-PV0, and then begins sampling and A/D
conversion. See Table 12 for settings of these bits. The default state is 000, indicating a 0s stabilization time. These
bits are the same whether reading or writing.
Table 12. Panel Voltage Stabilization Time Control
PV2
PV1
PV0
STABILIZATION TIME
0
0 sec. (default)
0
1
100 sec.
0
1
0
500 sec.
0
1
1 msec.
1
0
5 msec.
1
0
1
10 msec.
1
0
50 msec.
1
100 msec.
Bit 0
This bit is reserved. When read, it always reads as a zero.
DAC Control Register (Page 1, Address 02H)
The single bit in this register controls the power down control of the onboard digital-to-analog converter (DAC). This
register is formatted as follows:
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MSB
LSB
DPD
X
Bit 15 — DPD
28
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