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參數資料
| 型號： | TSC2300IPAGR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | GREEN, PLASTIC, TQFP-64 |
| 文件頁數： | 22/81頁 |
| 文件大?。?/td> | 1039K |
| 代理商： | TSC2300IPAGR |
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TSC2300
SLAS372 — NOVEMBER 2002
DAC Power Down. This bit controls whether the DAC is powered up and operational, or powered down. If the DAC is
powered down, the AOUT pin neither sinks nor sources current.
Table 13. DPD Bit Operation
DPD
VALUE
DESCRIPTION
0
DAC is powered and operational
1
DAC is powered down. (default)
Reference Register (Page 1, Address 03H)
This register controls whether the TSC2300 uses an internal or external reference, and if the internal reference is used,
the value of the reference voltage, whether it powers down between conversions and the programmable settling time
after reference power-up. This register is formatted as follows:
BIT 15
BIT
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 LSB
MSB
14
13
12
11
10
X
INT
DL1
DL0
PDN
RFV
Bit 4 —INT
Internal Reference Mode. If this bit is written to a 1, the TSC2300 uses its internal reference; if this bit is a 0, the part
assumes an external reference is being supplied. The default state for this bit is to select an external reference (0).
This bit is the same whether reading or writing.
Table 14. INT Bit Operation
INT
VALUE
DESCRIPTION
0
External reference selected (default)
1
Internal reference selected
Bits [3:2] — DL1, DL0
Reference Power-Up Delay. When the internal reference is powered up, a finite amount of time is required for the
reference to settle. If measurements are made before the reference has settled, these measurements are in error.
These bits allow for a delay time for measurements to be made after the reference powers up, thereby assuring that
the reference has settled. Longer delays are necessary depending upon the capacitance present at the VREFIN pin
(see Typical Curves). The delays are shown in Table 15. The default state for these bits is 00, selecting a 0
microsecond delay. These bits are the same whether reading or writing.
Table 15. Reference Power-Up Delay Settings.
DL1
DL0
DELAY TIME
0
0us (default)
0
1
100 s
1
0
500 s
1
1000 s
Bit 1 —PDN
Reference Power Down. If a 1 is written to this bit, the internal reference are powered down between conversions. If
this bit is a zero, the internal reference is powered at all times. The default state is to power down the internal
reference, so this bit will be a 1. This bit is the same whether reading or writing.
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