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參數資料
| 型號： | TSPC106AMGS83CG |
| 英文描述： | MEMORY CONTROLLER |
| 中文描述： | 內存控制器 |
| 文件頁數： | 17/40頁 |
| 文件大?。?/td> | 569K |
| 代理商： | TSPC106AMGS83CG |
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17
TSPC106
2102B
–
HIREL
–
02/02
PAR
Parity
1
O
Asserted indicates odd parity across the AD[31:0] and C/BE[3:0]
signals during address and data phases. Negated indicates even
parity.
I
Asserted indicates odd parity driven by another PCI master or the PCI
target during read data phases. Negated indicates even parity.
PERR
Parity error
1
O
Indicates that another PCI agent detected a data parity error.
I
Indicates that another PCI agent detected a data parity error.
PIRQ
Modified memory
interrupt request
1
O
In emulation mode (see
“
Address Maps
”
on page 19), indicates that a
PCI write has occurred to system memory that has not been recorded
by software.
REQ
PCI bus request
1
O
Indicates that the TSPC106 is requesting control of the PCI bus to
perform a transaction. Note that REQ is a point-to-point signal. Every
master has its own REQ signal.
SERR
System error
1
O
Indicates that an address parity error or some other system error
(where the result will be a catastrophic error) was detected.
I
Indicates that another target has detected a catastrophic error.
STOP
Stop
1
O
Indicates that the TSPC106, acting as the PCI target, is requesting that
the PCI bus master stop the current transaction.
I
Indicates that some other PCI agent is requesting that the PCI initiator
stop the current transaction.
TRDY
Target ready
1
O
Indicates that the TSPC106, acting as a PCI target, can complete the
current data phase of a PCI transaction. During a read, the TSPC106
asserts TRDY to indicate that valid data is present on AD[31:0]. During
a write, the TSPC106 asserts TRDY to indicate that it is prepared to
accept data.
I
Indicates that another PCI target is able to complete the current data
phase of a transaction.
Table 7.
PCI Interface Signals
Signal
Signal Name
Number of
Pins
I/O
Signal Description
相關PDF資料 |
PDF描述 |
|---|---|
| TSPC106AVGU66CE | MEMORY CONTROLLER |
| TSPC106AVGU66CG | MEMORY CONTROLLER |
| TSPC106AVGU83CE | MEMORY CONTROLLER |
| TSPC106AVGU83CG | MEMORY CONTROLLER |
| TSPC106AMG66CE | MEMORY CONTROLLER |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TSPC106AMGSB/Q66CE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY CONTROLLER |
| TSPC106AMGSB/Q66CG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY CONTROLLER |
| TSPC106AMGSB/Q83CE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY CONTROLLER |
| TSPC106AMGSB/Q83CG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY CONTROLLER |
| TSPC106AMGSB/T66CE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY CONTROLLER |
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