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參數資料
| 型號： | TVP5154PNPRG4 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER WITH INDEPENDENT SCALERS AND FAST LOCK |
| 中文描述： | 4通道低功耗PAL / NTSC制式/ SECAM制式，帶有獨立的定標器和視頻解碼器快速鎖定 |
| 文件頁數： | 16/78頁 |
| 文件大小： | 824K |
| 代理商： | TVP5154PNPRG4 |
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5.1 I
2
C Write Operation
5.2 I
2
C Read Operation
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
SLES163A–MARCH 2006–REVISED JULY 2006
Note, when register 0xFE is written to with any value, register 0xFF is set to 0x00. Likewise, when register
0xFF is written to with any value, register 0xFE is set to 0x00.
Data transfers occur utilizing the following illustrated formats.
An I
2
C master initiates a write operation to the TVP5154 decoder by generating a start condition (S)
followed by the TVP5154 I
2
C address (as shown below), in MSB first bit order, followed by a 0 to indicate
a write cycle. After receiving an acknowledge from the TVP5154 decoder, the master presents the
sub-address of the register, or the first of a block of registers it wants to write, followed by one or more
bytes of data, MSB first. The TVP5154 decoder acknowledges each byte after completion of each
transfer. The I
2
C master terminates the write operation by generating a stop condition (P).
abc
Step 1
I
2
C start (master)
0
S
Step 2
I
2
C general address (master)
7
1
6
0
5
1
4
1
3
1
2
0
1
X
0
0
Step 3
I
2
C acknowledge (slave)
9
A
Step 4
I
2
C write register address (master)
7
6
5
4
3
2
1
0
addr
addr
addr
addr
addr
addr
addr
addr
Step 5
I
2
C acknowledge (slave)
9
A
Step 6
I
2
C write data (master)
7
6
5
4
3
2
1
0
Data
Data
Data
Data
Data
Data
Data
Data
Step 7
(1)
I
2
C acknowledge (slave)
9
A
Step 8
I
2
C stop (master)
0
P
(1)
Repeat steps 6 and 7 until all data have been written.
The read operation consists of two phases. The first phase is the address phase. In this phase, an I
2
C
master initiates a write operation to the TVP5154 decoder by generating a start condition (S) followed by
the TVP5154 I
2
C address, in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving
acknowledges from the TVP5154 decoder, the master presents the sub-address of the register or the first
of a block of registers it wants to read. After the cycle is acknowledged, the master terminates the cycle
immediately by generating a stop condition (P).
The second phase is the data phase. In this phase, an I
2
C master initiates a read operation to the
TVP5154 decoder by generating a start condition followed by the TVP5154 I
2
C address (as shown below
for a read operation), in MSB first bit order, followed by a 1 to indicate a read cycle. After an acknowledge
from the TVP5154 decoder, the I
2
C master receives one or more bytes of data from the TVP5154
decoder. The I
2
C master acknowledges the transfer at the end of each byte. After the last data byte
desired has been transferred from the TVP5154 decoder to the master, the master generates a not
acknowledge followed by a stop.
16
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I
2
C Host Interface
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TVP5156PNP | 功能描述:視頻 IC 4Ch NTSC/PAL Video Decoder RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TVP5156PNPR | 功能描述:視頻 IC 4Ch NTSC/PAL Video Decoder RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TVP5157PNP | 功能描述:視頻 IC 4Ch NTSC/PAL Video Decoder RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TVP5157PNPR | 功能描述:視頻 IC 4Ch NTSC/PAL Video Decoder RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TVP5158 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:With Independent Scalers, Noise Reduction, Auto Contrast, and Flexible Output Formatter for Security and Other Multi-Channel Video Applications |
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