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Functional Description
4.1 Analog Front End
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
SLES163A–MARCH 2006–REVISED JULY 2006
TERMINAL
NAME
I/O
DESCRIPTION
NO.
100
77
58
39
95
76
57
38
122
HSYNC1
HSYNC2
HSYNC3
HSYNC4
VSYNC1 /PALI1
VSYNC2 /PALI2
VSYNC3 /PALI3
VSYNC4 /PALI4
PDN
O
Horizontal synchronization
O
1. VSYNC: Vertical synchronization
2. PALI: PAL line indicator or horizontal lock indicator. For the PAL line indicator, a 1
indicates a noninverted line, and a 0 indicates an inverted line.
I
Power down (active low). A 0 on this pin puts the decoder in standby mode. PDN preserves
the value of the registers.
Active-low reset. RESETB can be used only when PDN = 1. When RESETB is pulled low, it
resets all the registers and restarts the internal microprocessor.
I
2
C serial clock (open drain)
I
2
C serial data (open drain)
During power-on reset, this pin is sampled along with pin 117 (I2CA1) to determine the I
2
C
address the device is configured to. A 10-k
resistor should pull this either high (to IOVDD)
or low to select different I
2
C device addresses.
During power-on reset, this pin is sampled along with pin 118 (I2CA0) to determine the I
2
C
address the device is configured to. A 10-k
resistor should pull this either high (to IOVDD)
or low to select different I
2
C device addresses.
Unscaled system data clock at either 27 MHz or 54 MHz
RESETB
121
I
SCL
SDA
I2CA0
120
119
118
I/O
I/O
I
I2CA1
117
I
CLK1
CLK2
CLK3
CLK4
SCLK1
SCLK2
SCLK3
SCLK4
XIN/OSC
XOUT
103
84
61
42
104
85
62
43
124
123
O
O
Scaled system data clock at 27 MHz. This signal can be used to qualify scaled/unscaled
data when the unscaled system data clock is set to 54 MHz.
I
External clock reference. The user may connect XIN to an oscillator or to one terminal of a
crystal oscillator. The user may connect XOUT to the other terminal of the crystal oscillator
or not connect XOUT at all. One single 14.31818-MHz crystal or oscillator is needed for
ITU-R BT.601 sampling, for all supported standards.
Decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync for channel 1
Decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync for channel 2
Decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync for channel 3
Decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync for channel 4
Test-mode select. This pin should be connected to digital ground for correct device
operation.
O
CH1_OUT[7:0]
CH2_OUT[7:0]
CH3_OUT[7:0]
CH4_OUT[7:0]
TMS
105–112
86–93
67–74
48–55
36
O
O
O
O
I
Each channel of the TVP5154 decoder has an analog input channel that accepts two video inputs, which
should be ac coupled through 0.1-
μ
F capacitors. The decoder supports a maximum input voltage range of
0.75 V; therefore, an attenuation of one-half is needed for standard input signals with a peak-to-peak
variation of 1.5 V. The maximum parallel termination before the input to the device is 75
. Refer to
schematic at the end of this document for recommended configuration. The two analog input ports can be
connected as follows:
Two selectable composite video inputs or
One S-video input
An internal clamping circuit restores the ac-coupled video signal to a fixed dc level.
The programmable gain amplifier (PGA) and the automatic gain control (AGC) circuit work together to
ensure that the input signal is amplified or attenuated correctly, ensuring the proper input range for the
ADC.
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Functional Description
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