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參數資料
| 型號： | TVP5158PNP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP128 |
| 封裝： | GREEN, PLASTIC, HTQFP-128 |
| 文件頁數： | 61/108頁 |
| 文件大?。?/td> | 1395K |
| 代理商： | TVP5158PNP |
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SLES243E
– JULY 2009 – REVISED MARCH 2011
Table 4-25. AGC Gain Status
Subaddress
20h-21h
Default
Read Only
Subaddress
7
6
5
4
3
2
1
0
20h
Fine Gain [7:0]
21h
Reserved
Fine Gain [13:8]
These AGC gain status registers are updated automatically when the AGC is enabled; in manual gain control mode these register values
are not updated.
Since this register is a multi byte register it is necessary to "capture" the setting into the register to ensure that the value is not updated
between reading the lower and upper bytes. In order to cause this register to "capture" the current settings bit 0 of I2C register 24h (Status
Request) should be set to a 1. Once the internal processor has updated this register bit 0 of register 24h will be cleared, indicating that both
bytes of the AGC gain status register have been updated and can be read. Either byte may be read first since no further update will occur
until bit 0 of 24h is set to 1 again.
Table 4-26. Back-End AGC Status
Subaddress
23h
Default
Read Only
7
6
5
4
3
2
1
0
Gain [7:0]
Current back-end AGC ratio = Gain/128.
Table 4-27. Status Request
Subaddress
24h
Default
00h
7
6
5
4
3
2
1
0
Reserved
Capture
Setting a 1 in this register causes the inter processor to capture the current settings of the AGC status, noise measurement, and
the vertical line count registers. Since this capture is not immediate it is necessary to check for completion of the capture by
reading the "capture" bit repeatedly after setting it and waiting for it to be cleared by the internal processor. Once the "capture" bit
is 0 the AGC status, noise measurement and vertical line counters (20h/21h, 94h/95h and A2h/A3h) will have been updated, and
can be safely read in any order.
Table 4-28. AFE Gain Control
Subaddress
25h
Default
F5h
7
6
5
4
3
2
1
0
Reserved
ALC
Reserved
AGC
Reserved
For future compatibility, all reserved bits must be set to logic 1.
ALC
Active-high automatic level control (ALC) enable
0
ALC disabled (manual level control)
1
ALC enabled (default)
AGC
Active-high automatic gain control (AGC) enable
0
AGC disabled (manual gain control)
1
AGC enabled (default)
56
Internal Control Registers
Copyright
2009–2011, Texas Instruments Incorporated
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