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參數資料
| 型號： | TZA1047HL/M3 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.4 MM HEIGHT, PLASTIC, MS-026, SOT314-2, LQFP-64 |
| 文件頁數： | 7/69頁 |
| 文件大小： | 324K |
| 代理商： | TZA1047HL/M3 |
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9397 750 14664
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 1 June 2005
15 of 69
Philips Semiconductors
TZA1047
Preprocessor IC for CD and DVD rewritable
The RF amplier input supports many of the different signal congurations that are
produced by the various types of PDIC available. The possible input signals are either a
differential pair RFPIN and RFNIN which can be either currents or voltages, or two
single-ended voltages WRF and RRF.
7.6.1 Input section
The differential inputs RFPIN and RFNIN are connected to each other by programmable
termination resistors. These resistors provide a characteristic termination of the
connection to the OPU and convert current to voltage in the case of a current output PDIC
such as the TZA1045. The midpoint of these resistors is either connected to VREF
(bit REFON = 1) or is left oating (bit REFON = 0). The resistor values are 75
, 150 ,
300
or high-ohmic (> 5 k) and are selectable by word LDRF[1:0].
Both differential inputs can be used for read or write (bit DIFFR = 1, bit DIFFW = 1). Of the
single-ended inputs, RRF can be used for read (bit DIFFR = 0, signal r/w = 1) and WRF
for write (bit DIFFW = 0, signal r/w = 0). Depending on the setting of bit DIFFR and bit
DIFFW, the non-active inputs are disabled to save power. The single-ended input signals
are made differential by subtracting programmable reference voltages VWRF from WRF
and VRRF from RRF. Reference voltages VWRF and VRRF are programmable by word
VWRF[3:0] and word VRRF[3:0] respectively.
The control bit TSTVRF is intended for test purposes only and should be set to logic 0 for
normal operation.
7.6.2 Differential data path
The r/w multiplexer outputs one common differential RF signal for all possible modes,
which is amplied at a gain set by word GRFW[3:0] during write and a gain set by word
GRFR[3:0] during read.
A DC-control block allows the output signal to be DC-coupled to a channel decoder. The
relationship between input and output of the DC-control block is given by rfb =rfa DCRF.
Where DCRF is the RF DC control voltage controlled by word DCRF[5:0] set via the Fast
Serial Bus (FSB).
The DC control block has two functions: the rst function allows the output signal to be
DC-coupled to a channel decoder in which the DC control is adjusted in a closed-loop by
the decoder IC. This function requires both PDCRF and RDCRF bits to be set to logic 0.
The second function allows a DC offset calibration to be performed which is required if a
DC measurement for OPC is performed via the differential data path (BETA measurement
in PNX7850). For this purpose, the DC control polarity can be set by bit PDCRF and the
DAC accuracy can be increased (at the cost of decreasing the range) by setting bit
RDCRF. The relationship between input and output of the DC-control block is given by:
rfb = rfa DCRF, where
If bit PDCRF is logic 0, DCRF is subtracted from rfa; if bit PDCRF is logic 1, DCRF is added
to rfa. The step size is 10 mV when bit RDCRF = 0 and 5 mV when RDCRF = 1. The
control word DCRF[5:0] and bits PDCRF and RDCRF are set via the FSB.
A Variable Gain Amplier (VGA), also controlled via the FSB (word GRF[3:0]), is used to
create an AGC loop in conjunction with the decoder IC.
DC
RF
12
PDCRF
×
()
–
0.01
1
RDCRF
+
------------------------------
DCRF
×
=
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