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參數(shù)資料
| 型號： | U6057B |
| 英文描述： | Receiver for Point-to-Point Multiplex Systems |
| 中文描述： | 接收機(jī)點(diǎn)至點(diǎn)多路傳輸系統(tǒng) |
| 文件頁數(shù)： | 4/9頁 |
| 文件大小： | 89K |
| 代理商： | U6057B |
U6057B
TELEFUNKEN Semiconductors
Rev. A1, 03-Dec-97
Preliminary Information
4 (9)
recognizes the start-bit but decodes the second eight in-
formation bits.
There are several possibilities of cascading
CLK and DOUT are always connected in parallel.
Each shift register can be read-out individually by a
separate P/S line (see figure 5 ).
CLK and P/S are always connected in parallel.
DOUT
MASTER
and DOUT
SLAVE
are connected with
each other. The 16-bit data word can be read-out seri-
ally via DOUT
SLAVE
in one operation (see figure 6 )
Combinations with U6052B and U6057B (see fig-
ure 7)
Loading and Reading-out the Shift Register
Loading and reading-out of data from the shift register is
controlled by the three inputs DIN, CLK and P/S.
Input P/S = high
parallel operation
No data can be read-out from the shift register.
Data which arrive via the data line are stored in
the shift register. Output DOUT is disabled (high
resistance).
Input P/S = low
serial operation
The information available at DIN is transferred
to the shift register by the positive edge of CLK
and advanced by one position by each further
positive edge. The data word appears at DOUT.
The maximum clock frequency is 40 kHz.
The eighth flip-flop is a master – slave flip-flop. The
information of the eighth flip-flop is transferred to the
slave with each negative edge from CLK and is available
at the output DOUT.
DIN, CLK and EN are high-resistance inputs and process
a switching threshold of approximate 1.8 V. DOUT is an
open-collector output.
Input 4/2
The number of comparisons can be defined by the wiring
configuration of input 4/2.
4-fold comparison: Input 4/2 open
2-fold comparison: Input 4/2 connected to V
S
100
R
OSC
C
OSC
Data input
13274
Processor
V
Batt
100 F
510
1
2
16
15
18
17
3
4
U6057B
5
6
12
11
14
13
7
8
9
10
19
20
P/S
CLK
DOUT
SYN
Figure 3. Supplied with battery voltage
100
R
OSC
C
OSC
Data input
13275
Processor
5 V
1
2
16
15
18
17
3
4
U6057B
5
6
12
11
14
13
7
8
9
10
19
20
P/S
CLK
DOUT
SYN
Figure 4. Supplied with a stabilized 5-V voltage
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